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Siprj / sata-fpga

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how about the design? #1

Open Jzone315 opened 7 years ago

Jzone315 commented 7 years ago

I have tried a design on kintex7 using nysa_sata , but for now , only completed the oob , I think there maybe
bugs in the rtl code , some in the oob module have been corrected , others haven't been known , how about your design now , is there any progress in your working?

Siprj commented 7 years ago

I haven't got that far yet. I'm currently trying to make virtex5 GTP compatible with nysa_sata. Do you know for sure that there is bug in nysa_sata rtl? Because according their documentation they demonstrated working example on spartan6.

Jzone315 commented 7 years ago

I have just talked a while with the contributor , maybe it is the different platform caused my issues , i am not very sure for that. In my kintex7 platform , i have modified the tx_comm_reset and tx_comm_wake signals in oob_controller , making these two signals to hold up to 1.06us , while in the previous module they are valid only one clock cycle , this helped me completed the linkup now. For now , my issue is the signal sata_ready can't be assert , i haven't fixed that now , it has puzzled me for a long time.