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Siudya / ORB_FPGA

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More resources are used when project is rebuilt and synthesised #1

Closed jianyi324 closed 1 year ago

jianyi324 commented 4 years ago

Would you do me a favor? I need some help. It costed 139115 luts when the file called comDescriptor.cpp was synthesised. I followed your steps to rebuild vivado project， but i failed. Thanks!

Siudya commented 4 years ago

It doesn't matter. After implement and routing, it would be optimized. It would cost about 9000+ LUT.

------------------ 原始邮件 ------------------ 发件人: "jianyi324"<notifications@github.com>; 发送时间: 2020年7月25日(星期六) 晚上8:37 收件人: "Siudya/ORB_FPGA"<ORB_FPGA@noreply.github.com>; 抄送: "Subscribed"<subscribed@noreply.github.com>; 主题: [Siudya/ORB_FPGA] More resources are used when project is rebuilt and synthesised (#1)

Would you do me a favor? I need some help. It costed 139115 luts when the file called comDescriptor.cpp was synthesised. I followed your steps to rebuild vivado project， but i failed. Thanks!

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jianyi324 commented 4 years ago

555... I'm confused! Could you give me your email? I want to show you my picture about vivado project! Thanks!

Siudya commented 4 years ago

555.... 一开口就知道是中国人了 liangsen741@qq.com 你发这个吧

------------------ 原始邮件 ------------------ 发件人: "jianyi324"<notifications@github.com>; 发送时间: 2020年7月25日(星期六) 晚上9:30 收件人: "Siudya/ORB_FPGA"<ORB_FPGA@noreply.github.com>; 抄送: "梁森"<liangsen741@qq.com>; "Comment"<comment@noreply.github.com>; 主题: Re: [Siudya/ORB_FPGA] More resources are used when project is rebuilt and synthesised (#1)

555... I'm confused! Could you give me your email? I want to show you my picture about vivado project! Thanks!

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jianyi324 commented 4 years ago

Thank you very much!

albert7070 commented 4 years ago

comDescriptor_result I encountered the same problem, old brother. During comDescriptor synthesis, the Summary showed that the available resources FF and LUT on the chip exceeded a lot. as the picture shows:

Siudya commented 4 years ago

It doesn't matter. After implementing the cost will be optimized down to an acceptable level.

------------------ 原始邮件 ------------------ 发件人: "Albert"<notifications@github.com>; 发送时间: 2020年8月9日(星期天) 上午10:39 收件人: "Siudya/ORB_FPGA"<ORB_FPGA@noreply.github.com>; 抄送: "梁森"<liangsen741@qq.com>; "Comment"<comment@noreply.github.com>; 主题: Re: [Siudya/ORB_FPGA] More resources are used when project is rebuilt and synthesised (#1)

I encountered the same problem, old brother. During comDescriptor synthesis, the Summary showed that the available resources FF and LUT on the chip exceeded a lot. as the picture shows:

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albert7070 commented 4 years ago

According to the code, I have copied the .bit and .hwh files to the corresponding locations. Then, a problem occurred. First, the .bit file is successfully loaded, and you can see that the overlay object has 4 IP Blocks: axi_dma_FAST; axi_dma_Gaus; axi_dma_des_2Mem; axi_intc_0. Jupyter_error1 However, when calling IP Blocks whose type is pynq.lib.dma.DMA, an error will occur (take FAST as an example): Jupyter_error2 Jupyter_error3 Have you encountered similar problems? my old brother.

Siudya commented 4 years ago

Sorry but I never encounter the problem. Did you use pynq 2.4 or higher with the .bit and .hwh files provided in the repo? Maybe a rebooting can make it work :P .

------------------ 原始邮件 ------------------ 发件人: "Albert"<notifications@github.com>; 发送时间: 2020年8月13日(星期四) 晚上8:13 收件人: "Siudya/ORB_FPGA"<ORB_FPGA@noreply.github.com>; 抄送: "梁森"<liangsen741@qq.com>; "Comment"<comment@noreply.github.com>; 主题: Re: [Siudya/ORB_FPGA] More resources are used when project is rebuilt and synthesised (#1)

According to the code, I have copied the .bit and .hwh files to the corresponding locations. Then, a problem occurred. First, the .bit file is successfully loaded, and you can see that the overlay object has 4 IP Blocks: axi_dma_FAST; axi_dma_Gaus; axi_dma_des_2Mem; axi_intc_0.

However, when calling IP Blocks whose type is pynq.lib.dma.DMA, an error will occur (take FAST as an example):

Have you encountered similar problems? my old brother.

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Silentstreet commented 4 years ago

@albert7070 我也碰到了这个问题。但是如果是加载他的bit的话，就可以。但是自己重建的vivado工程产生的bit就没法加载出来。有意交流的话可以邮箱fastcorner@163.com。

albert7070 commented 4 years ago

old brother,Sorry to disturb you. I could not find the constraint xdc file of the vivado project in the pynq_arch folder. I really want to figure out how the pin constraints of your project are allocated.

Siudya commented 4 years ago

No contraints are needed. All the pins are set via board files. (only sysclk is connected to a PL pin)