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Siudya / ORB_FPGA

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Generating the bitstream #3

Closed srinivasans74 closed 1 year ago

srinivasans74 commented 3 years ago

Usually once the HLS synthesis is finished did you autoconnect the ip in vivado ? or did you do the place and route of the ip?

Siudya commented 3 years ago

You can run pynq_arch.tcl to rebuild the project. No need to do it manually.