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Siudya / ORB_FPGA

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NO TOP Module #5

Closed lanyangyang closed 1 year ago

lanyangyang commented 1 year ago

After following the given step of rebuild project in vivado, I try to generate bitstream. However, I received the following error, [Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top <name> [current_fileset]). Are there any help??

Siudya commented 1 year ago

Did you create rtl wrapper for the block design? Vivado should automatically pick top module. In Vivado GUI，you can right click the .bd file and click "create HDL wrapper" and then simply choose auto-update. Hope it can help.