search

Siudya / ORB_FPGA

67 stars 27 forks source link

Final design is overutilizing the resources when rebuilding #7

Closed ananyaverma2 closed 6 months ago

ananyaverma2 commented 7 months ago

As mentioned by a few people, the HLS IPs are overutilizing the resources present on the PYNQ Z2 board, and should resolve when generating bitstream. However the final design is still overutilizing the resources resulting in failed implementation.

ananyaverma2 commented 6 months ago

Final design works for Vivado 2018.3, but not for vivado 2022.2 (resource overutilization)