When moving segment register (two bytes), for instance ES, to register (four bytes), it is invalidly padded. According to the Intel manual, "When executing MOV Reg, Sreg, the processor copies the content of Sreg to the 16 least significant bits of the
general-purpose register. The upper bits of the destination register are zero for most IA-32 processors [...]"
Description
When moving segment register (two bytes), for instance
ES
, to register (four bytes), it is invalidly padded. According to the Intel manual, "When executingMOV Reg, Sreg
, the processor copies the content ofSreg
to the 16 least significant bits of the general-purpose register. The upper bits of the destination register are zero for most IA-32 processors [...]"Reference: Ref. Intel 64 and IA-32 Architecture Software Developer's Manual Vol. 2B 4-35
Affected instructions:
Reproduction guide
Instruction:
Input:
Observed output:
Expected output:
EAX
set with correct paddding.System Info
OS:
BINSEC: 20170301 0.1