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SonalPinto / kronos

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
https://sonalpinto.github.io/kronos/#/
Apache License 2.0
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Bug report: Reading existent CSRs cause the CPU to hang in some microarchitectural conditions #8

Open flaviens opened 1 year ago

flaviens commented 1 year ago

Hi there!

In complement to #7 , I noticed that reading existing CSRs also causes the CPU to hang. This happens only if the destination register is distinct from zero.

For example, in the snippet below, zero is never written to address zero.

  .section ".text.init","ax",@progbits
  .globl _start
  .align 2
_start:

  csrrw x1, mtvec, zero

  nop

  sw zero, (zero)

infinite_loop0:
  j infinite_loop0

This does not happen in all cases, for example this snippet is fine, probably because the CSR register write signal is (legitimately) overwritten with 0 just after the first register write occurred.

  .section ".text.init","ax",@progbits
  .globl _start
  .align 2
_start:

  csrrw x1, mtvec, zero
  csrw medeleg, zero

  nop

  sw zero, (zero)

infinite_loop0:
  j infinite_loop0

It is possible that the bug only has symptoms when #6 is implemented (I haven't double checked that, since #6 or any such alternative is necessary for RISC-V compliance).

Thanks!