Program dissemination through memory hierarchy

[asultan123]

• Need to instantiate memory hierarchy for yet to be modeled processor
• Given simplistic tree, need to figure out timings for program dissemination from root to leafs
• Likely to be simple tree walk algorithm with aggregate timings (but what about arbitrary trees?)
• Timings used for builtin programs tied to individual DMAs to allow for fetching programs from attached SRAMS
• Need to actually define baseline program that pulls instructions from SRAMs (timed wait then transfer but special transfer?)
• I'll solve this problem for a rigid hierarchy and see what I learn. What the actual algorithm I applied is (fun shit to speed up, why not use thrust for GPU speedup?)

[asultan123]

Realization

Since it was assumed that the S2MM DMAS are write only loading their program info can be done on the fly when the corresponding MM2S in the link sends the program. This can't work for MM2S stream outputs that flow through compute nodes. An alternative is to just load the program after storing it as a regular payload. Here are the pros and cons of each position.

S2MM load program on the fly

Pros

• Faster
• Reduces sink memory pressure (if there is limit on number of active ports)

Cons

• Harder to Model
• Need extra wire to identify program data and not generic data for in buffer storage rather than data to be stored (need extra wire)
• Complicates both S2MM and MM2S control logic
• Transition from self program data to generic payload is cumbersome because the sudden switch implies that the S2MM DMA will suddenly start executing it's just loaded program as soon as the payload type switch happens. This means that it would need to buffer incoming data in anticipation of that event (greatly complicates timing estimation for program decimination) or the data flag type flag signal will need to be async (parts of design will not be fully async)
• Only applies to S2MM DMAs and thus asymmetry between MM2S and S2MM

S2MM load program after store

Pros

• Easier timing estimation
• Easier to immediately model
• No need to define payload type so no extra wire
• avoids transition problem
• No asymmetry between MM2S and S2MM in terms of programming methodology (can use hardcoded program to "program")

Cons

• Slower
• Port attached becomes read/write

[asultan123]

Needs to be rewritten entirely based on transition from DMAs to SRAMs with address generators