Open hmeijdam opened 1 year ago
Took some time during lunch to narrow this down. Breaking change seemed to occur @ e8209f4f3eea812609237ebdc88699a8f7c0f9b9 If you can get passed the compilation error on the '85 here, you'll see bad clocking. But not at the commit previous: 579388e3610e5a2a19546eb7356df928dc90eb0e
Please use supplied patch and confirm things are working again. I don't know if the patch is technically what we want, but it sure makes the waveforms better. Note the boards.txt changes- it requires a restart of the IDE and a reflash of the bootloader to set the fuses. 0001-Fix-up-clocks-4mhz.patch
While playing with the ADC clock and the USI 4-bit timer, I noticed odd things at 4MHz clock speed when using V2.0.0. Then I noticed that delay() was also off at 4MHz.
This sketch should demonstrate the issue, as it's supposed to produces 100Hz on PB1 at 16, 8, 4, 2 and 1MHz
The results are:
16MHz PLL : 100Hz 8MHz internal osc : 100Hz 4MHz internal osc : 25Hz 2MHz internal osc : 50Hz 1MHz internal osc : 100Hz
I looked in wiring.c if i could see something obvious going wrong with the clock prescaling but could not find a cause.
I suspected it has to do with clock prescaling, because the ADC clock (manually prescaled by me) also slowed down by a factor 8 while I expected a factor 2 when I switched from 8MHz to 4MHz.
On the board managers release 1.5.2 the delay worked fine and I got 100Hz on all clock frequencies.