Christian-B
commented
2 years ago Virtual vertices are handled directly rather than allocating them to a place on the machine (i.e. they are dealt with by routing down the link to them from the real chip rather than adding a virtual chip).
Added a check to Chip to make sure this is 100% true! if virtual: raise NotImplementedError("Unexpected use of virtual chip")
if that passes need an issue to remove Virtual Chips.
Reduce the memory footprint and improve the operation with new algorithms. Includes: 1) Drop some constraints that no longer make sense or are not used. 2) Deal with iteration of keys elsewhere (as it is always the same anyway) 3) There is no machine graph! There are still machine objects linked though. 4) Edge partitions can exist outside of graphs (indeed machine partitions are now used directly in splitters) 5) Splitters now handle same-chip-as "constraint" through explicit grouping obtained by calling a method (this means that things to go on the same chip must be handled by a single splitter, but this was already the case in all examples). 6) Splitters can filter their incoming vertices to match with a source. This takes on the equivalent role of filtering edges. 7) There is a new placer that ensures that vertices are placed on chips adjacent to each other. This is needed by the new routing algorithm so all other placers have been removed! 8) There is a new routing algorithm that takes advantage of the placer above, and also makes edges from the same source application vertex take the same path to their destinations. Other routing algorithms are still available because there is no further downstream issues. 9) Some compression of routing can be done on routing table generation. This compresses adjacent keys with the same route. 10) Routing information generation is always done per-application vertex, though some additional per-machine-vertex information is also produced. Both exist downstream. Other routing information algorithms have been removed. 11) Partitioning is always done to max_atoms_per_core. Placement will fail if this is not good enough. 12) Partitioning uses a much simpler "chip counter" to estimate boards required (which appears more successful than master despite its simplicity). 13) Virtual vertices are handled directly rather than allocating them to a place on the machine (i.e. they are dealt with by routing down the link to them from the real chip rather than adding a virtual chip). 14) Some useful functions have been added to placements which are now ordered by chip. 15) Routing tables have additional checks to ensure they don't contain both application and machine versions of a vertex (which can be fatal). 16) Lots of data structures have been removed and their consequences dealt with (removing functions, using different ordering etc.).
Depends on SpiNNakerManchester/SpiNNMachine#175