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SpiNNakerManchester / spio

A library of FPGA designs and re-usable modules for I/O and internal connectivity in SpiNNaker systems.
BSD 3-Clause "New" or "Revised" License
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Verify Raggedstone FTDI design UART buffer size choice. #13

Open mossblaser opened 10 years ago

mossblaser commented 10 years ago

Must check to see that the chosen buffer size is adequate for flow control purposes (i.e. no TX packets are dropped in normal circumstances).

Christian-B commented 4 years ago

So old assuming will not fix.

Please reopen if this is incorrect with an explanation as to why it still needs fixing.