Psync snd rcv ft

[lplana]

This commit incorporates 2 major changes:

• new sender and receiver modules that operate in stac mode(synchronous timing, asynchronous control). This doubles the throughput on FPGA <-> SpiNNaker links.
• the top level has been modified to move the synchronisers on link signals into the sender and receiver modules. This allows a simpler substitution of these modules with fully asynchronous implementations that do not require synchronisers at the top level.

[mossblaser]

Glancing around and things seem to look sane, though I'm only really remotely qualified to scan over the top-level, packet counters etc. so that is mostly where I've been looking carefully. Are there any specific places in the implementation that would be useful for me to look at in more detail?

The comment/citation for the predictive stuff seems sensible.

If I'm reading things right the only thing remaining is that the documentation for the SPI registers in https://github.com/SpiNNakerManchester/spio/tree/psync_snd_rcv_ft/designs/spinnaker_fpgas could do with updating to account for the new "tpX" registers. Feel free to switch the listings to a more compact representation table format... ;)