Packets which are intended to be routed off to peripherals but are emergency routed will show up in the FPGAs in the wrong place, possibly even the wrong FPGA. A strategy needs to be developed to handle this as at present such packets will inevitably be misrouted (possibly being left inside SpiNNaker to loop around the torus forever...).
Packets which are intended to be routed off to peripherals but are emergency routed will show up in the FPGAs in the wrong place, possibly even the wrong FPGA. A strategy needs to be developed to handle this as at present such packets will inevitably be misrouted (possibly being left inside SpiNNaker to loop around the torus forever...).