Open Bill94l opened 2 months ago
Hi,
The PMP isn't implemented in Naxriscv (at all) I guess on legal implementation would be to hardwire all the PMP relater CSR to zero, right ?
I use SocSim+RVLS which normally takes into account that the pmp is not implemented in the DUT and spike https://github.com/SpinalHDL/rvls/blob/520b40dc9bc4d15348dd2225a7c4fd30ebf900de/src/hart.cpp#L130
Why don't we get the same behaviour when the DUT and Spike are running? Why does spike not trigger a trap? It is configured not to support PMP.
After updating my RISC-V-DV locally, this problem no longer occurs. This is because it takes into account that the PMP is not implemented.
Ahhhh ok ^^ So, overall, you use the python of RISC-V-DV to generate a instruction stream right ? How painfull is it to use / setup ?
In fact, you would need questa-sim licence to use UVM to generate random programs. I spent a lot of time setting up the environment. If I find any bugs, I will let you know.
Do you have a problem with the use of non-open source tools? (when Verilator supports UVM, it can replace Questasim) I have seen that you are interested in the use of a fuzzing tool for VexiiRiscv. Let me know if you are interested in incorporating RISC V-DV into NaxRiscv to have a solid verification environment?
In fact, you would need questa-sim licence to use UVM to generate random programs. I spent a lot of time setting up the environment
Very sad that open-source project are locked behind paywals like this :( Wasn't there some python generation for random program aswell ? or that one is not great ?
Do you have a problem with the use of non-open source tools?
Yes :
Let me know if you are interested in incorporating RISC V-DV into NaxRiscv to have a solid verification environment?
As long as verilator doesn't support it, i would say i can't use it, or maybe we could generate batches of instruction stream into files and upload them somewere ? But that may generate too much data to get proper coverage XD
Wasn't there some python generation for random program aswell ? or that one is not great ?
Riscv-dv is a SV/UVM based instruction generator, so in order to generate random programs, the riscv-dv Python script needs a simulator that supports UVM. I think it's possible to use a simulator called pyflow, but I haven't tried it yet
maybe we could generate batches of instruction stream into files and upload them somewere ? But that may generate too much data to get proper coverage XD
This could be an alternative solution, I will have to see how to guarantee the coverage and the amount of data that will be generated
Riscv-dv is a SV/UVM based instruction generator, so in order to generate random programs, the riscv-dv Python script needs a simulator that supports UVM.
Ahhhhh saaaaaad
I think it's possible to use a simulator called pyflow, but I haven't tried it yet
Never heard of it :)
Hi Charles,
Now I have RISCV-DV integrated with NaxRiscv. This allows me to do fuzzing by generating random programs and start lockstep execution with RVLS via SocSim.
After running a program generated by riscv-dv for rv64imafdc, I see that reading the pmpcfg0 register through csrr triggers a trap in the DUT but not in spike. Here is the execution result :
Spike log:
Tracer log:
Everything you need to debug or reproduce the execution is in the attached file : debug_riscv-dv.zip