Open Bill94l opened 2 months ago
Hi,
i think this is the combination of a few things :
Maybe the best would be to provide NaxRiscv generation with instead of ioRange = a => a(31 downto 28) === 0x1 having ioRange = a => !a(31)
That way only rv region add 0 0 0000000080000000 0000000080000000 would be considered as cached by Nax and everything else would be sensitive to access faults. And so should be in sync with rvls.
ioRange = a => !a(31)
Once this change has been made, the test becomes infinite: it loops between "trap_store_access_fault" and "trap_store_address_misaligned"
[info] Sim starting <3
^C
[warn] Canceling execution...
Spike log
core 0: 0x0000000080004000 (0x0400006f) j pc + 0x40
core 0: 3 0x0000000080004000 (0x0400006f)
core 0: 0x0000000080004040 (0x00001671) c.addi a2, -4
core 0: 3 0x0000000080004040 (0x1671) x12 0x0000000080000004
core 0: 0x0000000080004042 (0x0000e21c) c.sd a5, 0(a2)
core 0: exception trap_store_address_misaligned, epc 0x0000000080004042
core 0: tval 0x0000000080000004
core 0: 0x0000000080004000 (0x0400006f) j pc + 0x40
core 0: 3 0x0000000080004000 (0x0400006f)
core 0: 0x0000000080004040 (0x00001671) c.addi a2, -4
core 0: 3 0x0000000080004040 (0x1671) x12 0x0000000080000000
core 0: 0x0000000080004042 (0x0000e21c) c.sd a5, 0(a2)
core 0: 3 0x0000000080004042 (0xe21c) mem 0x0000000080000000 0x000000007fffff08
core 0: 0x0000000080004044 (0x000607b3) add a5, a2, zero
core 0: 3 0x0000000080004044 (0x000607b3) x15 0x0000000080000000
core 0: 0x0000000080004048 (0xf0078793) addi a5, a5, -256
core 0: 3 0x0000000080004048 (0xf0078793) x15 0x000000007fffff00
core 0: 0x000000008000404c (0x0017b423) sd ra, 8(a5)
core 0: exception trap_store_access_fault, epc 0x000000008000404c
core 0: tval 0x000000007fffff08
core 0: 0x0000000080004000 (0x0400006f) j pc + 0x40
core 0: 3 0x0000000080004000 (0x0400006f)
core 0: 0x0000000080004040 (0x00001671) c.addi a2, -4
core 0: 3 0x0000000080004040 (0x1671) x12 0x000000007ffffffc
core 0: 0x0000000080004042 (0x0000e21c) c.sd a5, 0(a2)
core 0: exception trap_store_address_misaligned, epc 0x0000000080004042
core 0: tval 0x000000007ffffffc
core 0: 0x0000000080004000 (0x0400006f) j pc + 0x40
core 0: 3 0x0000000080004000 (0x0400006f)
core 0: 0x0000000080004040 (0x00001671) c.addi a2, -4
core 0: 3 0x0000000080004040 (0x1671) x12 0x000000007ffffff8
core 0: 0x0000000080004042 (0x0000e21c) c.sd a5, 0(a2)
core 0: exception trap_store_access_fault, epc 0x0000000080004042
core 0: tval 0x000000007ffffff8
core 0: 0x0000000080004000 (0x0400006f) j pc + 0x40
core 0: 3 0x0000000080004000 (0x0400006f)
core 0: 0x0000000080004040 (0x00001671) c.addi a2, -4
core 0: 3 0x0000000080004040 (0x1671) x12 0x000000007ffffff4
core 0: 0x0000000080004042 (0x0000e21c) c.sd a5, 0(a2)
core 0: exception trap_store_address_misaligned, epc 0x0000000080004042
core 0: tval 0x000000007ffffff4
core 0: 0x0000000080004000 (0x0400006f) j pc + 0x40
core 0: 3 0x0000000080004000 (0x0400006f)
core 0: 0x0000000080004040 (0x00001671) c.addi a2, -4
core 0: 3 0x0000000080004040 (0x1671) x12 0x000000007ffffff0
core 0: 0x0000000080004042 (0x0000e21c) c.sd a5, 0(a2)
core 0: exception trap_store_access_fault, epc 0x0000000080004042
core 0: tval 0x000000007ffffff0
core 0: 0x0000000080004000 (0x0400006f) j pc + 0x40
core 0: 3 0x0000000080004000 (0x0400006f)
core 0: 0x0000000080004040 (0x00001671) c.addi a2, -4
core 0: 3 0x0000000080004040 (0x1671) x12 0x000000007fffffec
core 0: 0x0000000080004042 (0x0000e21c) c.sd a5, 0(a2)
core 0: exception trap_store_address_misaligned, epc 0x0000000080004042
core 0: tval 0x000000007fffffec
Separate issue: Does nax support unaligned instructions?
Once this change has been made, the test becomes infinite: it loops between "trap_store_access_fault" and "trap_store_address_misaligned"
As spike do agree with that behaviour, i would say that it is either OK, either that is the riscv-dv configuration/generation which need tweeks to avoid this.
Separate issue: Does nax support unaligned instructions?
No it doesn't, when running linux, opensbi emulate them in machine mode.
In this case :
you are going to make a commit to modify ioRange = a => a(31 downto 28) === 0x1
by ioRange = a => !a(31)
in the following files or it is not necessary ?
I think that would be great, PR welcome :)
Hi,
After running a program generated by riscv-dv for rv64imafdc, accessing address 0x7fffff20 generates an exception (trap_store_access_fault) in spike, but the DUT does the commit and RVLS detects a commit error. Here is the error message during execution
Dump
Spike log
Tracer log
Everything you need to debug or reproduce the execution is in the attached file: debug_riscv-dv2.zip