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SpinalHDL / NaxRiscv

MIT License
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Memory address level traces #35

Open Pavitra07 opened 1 year ago

Pavitra07 commented 1 year ago

Can I generate a simulation trace that includes the memory addresses of the instructions executed, along with the information if it was a cache hit or miss?

Dolu1990 commented 1 year ago

Can I generate a simulation trace that includes the memory addresses of the instructions executed

You can by using the spike logs as reference. Add the argument : --trace-ref This will generate a log file You may have more info if you also add --spike-debug

along with the information if it was a cache hit or miss?

Not implemented yet.