compiling code with updated codes

full output of console is here


hsubedi@kronos:~/instruction_test_bed/litex/fpga_nax_3$ python3 -m litex_boards.targets.digilent_arty --variant a7-100           --cpu-type naxriscv --xlen 64 --cpu-count 1 --l2-bytes 4096         --update-repo no --build
Namespace(toolchain='vivado', build=True, load=False, log_filename=None, log_level='info', flash=False, variant='a7-100', sys_clk_freq=100000000.0, with_xadc=False, with_dna=False, with_ethernet=False, with_etherbone=False, eth_ip='192.168.1.50', eth_dynamic_ip=False, with_spi_sdcard=False, with_sdcard=False, sdcard_adapter=None, with_spi_flash=False, with_pmod_gpio=False, output_dir=None, gateware_dir=None, software_dir=None, include_dir=None, generated_dir=None, build_backend='litex', no_compile=False, no_compile_software=False, no_compile_gateware=False, soc_csv=None, soc_json=None, soc_svd=None, memory_x=None, doc=False, bios_lto=False, bios_console='full', bus_standard='wishbone', bus_data_width=32, bus_address_width=32, bus_timeout=1000000, bus_bursting=False, bus_interconnect='shared', cpu_type='naxriscv', cpu_variant=None, cpu_reset_address=None, cpu_cfu=None, no_ctrl=False, integrated_rom_size=131072, integrated_rom_init=None, integrated_sram_size=8192, integrated_main_ram_size=None, csr_data_width=32, csr_address_width=14, csr_paging=2048, csr_ordering='big', ident=None, no_ident_version=False, no_uart=False, uart_name='serial', uart_baudrate=115200, uart_fifo_depth=16, with_uartbone=False, with_jtagbone=False, jtagbone_chain=1, no_timer=False, timer_uptime=False, l2_size=8192, synth_mode='vivado', vivado_synth_directive='default', vivado_opt_directive='default', vivado_place_directive='default', vivado_post_place_phys_opt_directive=None, vivado_route_directive='default', vivado_post_route_phys_opt_directive='default', vivado_max_threads=None, scala_file=None, scala_args=None, xlen='64', cpu_count='1', with_coherent_dma=False, with_jtag_tap=False, with_jtag_instruction=False, update_repo='no', no_netlist_cache=False, with_fpu=False, l2_bytes='4096', l2_ways=8)
INFO:S7PLL:Creating S7PLL, speedgrade -1.
INFO:S7PLL:Registering Single Ended ClkIn of 100.00MHz.
INFO:S7PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut1 eth of 25.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut2 sys4x of 400.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut3 sys4x_dqs of 400.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut4 idelay of 200.00MHz (+-10000.00ppm).
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2023-10-27 16:46:33)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7a100tcsg324-1.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU naxriscv added.
INFO:SoC:CPU naxriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU naxriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU naxriscv setting reset address to 0x00000000.
INFO:SoC:CPU naxriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 Bus adapted from AXI-Lite 32-bit to Wishbone 32-bit.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoC:CPU naxriscv adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU naxriscv adding SoC components.
INFO:SoCCSRHandler:uart CSR added at Location 2.
INFO:SoCCSRHandler:timer0 CSR added at Location 3.
INFO:SoCBusHandler:opensbi Region added at Origin: 0x40f00000, Size: 0x00080000, Mode: RW, Cached: True Linker: True.
INFO:SoCBusHandler:plic Region added at Origin: 0xf0c00000, Size: 0x00400000, Mode: RW, Cached: False Linker: True.
INFO:SoCBusHandler:clint Region added at Origin: 0xf0010000, Size: 0x00010000, Mode: RW, Cached: False Linker: True.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: RX, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: RX, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 1.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 2.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RWX, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (1 <-> 4).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 1.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 4.
INFO:SoCCSRHandler:leds CSR allocated at Location 5.
INFO:SoCCSRHandler:sdram CSR allocated at Location 6.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (7)
rom                 : Origin: 0x00000000, Size: 0x00020000, Mode: RX, Cached: True Linker: False
sram                : Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached: True Linker: False
main_ram            : Origin: 0x40000000, Size: 0x10000000, Mode: RWX, Cached: True Linker: False
opensbi             : Origin: 0x40f00000, Size: 0x00080000, Mode: RW, Cached: True Linker: True
csr                 : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
clint               : Origin: 0xf0010000, Size: 0x00010000, Mode: RW, Cached: False Linker: True
plic                : Origin: 0xf0c00000, Size: 0x00400000, Mode: RW, Cached: False Linker: True
Bus Masters: (1)
- cpu_bus0
Bus Slaves: (4)
- rom
- sram
- main_ram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (7)
- ctrl           : 0
- ddrphy         : 1
- uart           : 2
- timer0         : 3
- identifier_mem : 4
- leds           : 5
- sdram          : 6
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (3)
- noirq  : 0
- uart   : 1
- timer0 : 2
INFO:SoC:--------------------------------------------------------------------------------
INFO:S7PLL:Config:
divclk_divide : 1
clkout0_freq  : 100.00MHz
clkout0_divide: 16
clkout0_phase : 0.00°
clkout1_freq  : 25.00MHz
clkout1_divide: 64
clkout1_phase : 0.00°
clkout2_freq  : 400.00MHz
clkout2_divide: 4
clkout2_phase : 0.00°
clkout3_freq  : 400.00MHz
clkout3_divide: 4
clkout3_phase : 90.00°
clkout4_freq  : 200.00MHz
clkout4_divide: 8
clkout4_phase : 0.00°
vco           : 1600.00MHz
clkfbout_mult : 16
NaxRiscv netlist : NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:SoC Hierarchy:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:
BaseSoC
└─── crg (_CRG)
│    └─── pll (S7PLL)
│    │    └─── [FDCE]
│    │    └─── [BUFG]
│    │    └─── [PLLE2_ADV]
│    │    └─── [FDCE]
│    │    └─── [BUFG]
│    │    └─── [FDCE]
│    │    └─── [FDCE]
│    │    └─── [BUFG]
│    │    └─── [FDCE]
│    │    └─── [BUFG]
│    │    └─── [FDCE]
│    │    └─── [BUFG]
│    │    └─── [FDCE]
│    │    └─── [FDCE]
│    └─── idelayctrl (S7IDELAYCTRL)
│    │    └─── [IDELAYCTRL]
└─── bus (SoCBusHandler)
│    └─── axilite2wishbone_0* (AXILite2Wishbone)
│    │    └─── fsm (FSM)
│    └─── _interconnect (InterconnectShared)
│    │    └─── arbiter (Arbiter)
│    │    │    └─── rr (RoundRobin)
│    │    └─── decoder (Decoder)
│    │    └─── timeout (Timeout)
│    │    │    └─── waittimer_0* (WaitTimer)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── ctrl (SoCController)
└─── cpu (NaxRiscv)
│    └─── soc_bus (SoCBusHandler)
│    │    └─── axilite2wishbone_0* (AXILite2Wishbone)
│    │    │    └─── fsm (FSM)
│    │    └─── _interconnect (InterconnectShared)
│    │    │    └─── arbiter (Arbiter)
│    │    │    │    └─── rr (RoundRobin)
│    │    │    └─── decoder (Decoder)
│    │    │    └─── timeout (Timeout)
│    │    │    │    └─── waittimer_0* (WaitTimer)
│    └─── [NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009]
└─── rom (SRAM)
└─── sram (SRAM)
└─── identifier (Identifier)
└─── uart_phy (RS232PHY)
│    └─── tx (RS232PHYTX)
│    │    └─── clk_phase_accum (RS232ClkPhaseAccum)
│    │    └─── fsm (FSM)
│    └─── rx (RS232PHYRX)
│    │    └─── clk_phase_accum (RS232ClkPhaseAccum)
│    │    └─── fsm (FSM)
└─── uart (UART)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
│    │    └─── eventsourceprocess_1* (EventSourceProcess)
│    └─── tx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
│    └─── rx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
└─── timer0 (Timer)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
└─── ddrphy (A7DDRPHY)
│    └─── tappeddelayline_0* (TappedDelayLine)
│    └─── dqspattern_0* (DQSPattern)
│    └─── bitslip_0* (BitSlip)
│    └─── bitslip_1* (BitSlip)
│    └─── bitslip_2* (BitSlip)
│    └─── bitslip_3* (BitSlip)
│    └─── tappeddelayline_1* (TappedDelayLine)
│    └─── bitslip_4* (BitSlip)
│    └─── bitslip_5* (BitSlip)
│    └─── bitslip_6* (BitSlip)
│    └─── bitslip_7* (BitSlip)
│    └─── bitslip_8* (BitSlip)
│    └─── bitslip_9* (BitSlip)
│    └─── bitslip_10* (BitSlip)
│    └─── bitslip_11* (BitSlip)
│    └─── bitslip_12* (BitSlip)
│    └─── bitslip_13* (BitSlip)
│    └─── bitslip_14* (BitSlip)
│    └─── bitslip_15* (BitSlip)
│    └─── bitslip_16* (BitSlip)
│    └─── bitslip_17* (BitSlip)
│    └─── bitslip_18* (BitSlip)
│    └─── bitslip_19* (BitSlip)
│    └─── bitslip_20* (BitSlip)
│    └─── bitslip_21* (BitSlip)
│    └─── bitslip_22* (BitSlip)
│    └─── bitslip_23* (BitSlip)
│    └─── bitslip_24* (BitSlip)
│    └─── bitslip_25* (BitSlip)
│    └─── bitslip_26* (BitSlip)
│    └─── bitslip_27* (BitSlip)
│    └─── bitslip_28* (BitSlip)
│    └─── bitslip_29* (BitSlip)
│    └─── bitslip_30* (BitSlip)
│    └─── bitslip_31* (BitSlip)
│    └─── bitslip_32* (BitSlip)
│    └─── bitslip_33* (BitSlip)
│    └─── bitslip_34* (BitSlip)
│    └─── bitslip_35* (BitSlip)
│    └─── tappeddelayline_2* (TappedDelayLine)
│    └─── tappeddelayline_3* (TappedDelayLine)
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [IOBUF]
│    └─── [ISERDESE2]
│    └─── [ISERDESE2]
│    └─── [OSERDESE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [IOBUF]
│    └─── [ISERDESE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [ISERDESE2]
│    └─── [OSERDESE2]
│    └─── [IDELAYE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [ISERDESE2]
│    └─── [ISERDESE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [IDELAYE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [ISERDESE2]
│    └─── [IDELAYE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [IOBUFDS]
│    └─── [IOBUF]
│    └─── [ISERDESE2]
│    └─── [ISERDESE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [ISERDESE2]
│    └─── [OSERDESE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [OBUFDS]
│    └─── [IOBUFDS]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [ISERDESE2]
│    └─── [OSERDESE2]
│    └─── [IDELAYE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [IOBUF]
│    └─── [OSERDESE2]
│    └─── [OSERDESE2]
│    └─── [ISERDESE2]
│    └─── [IDELAYE2]
│    └─── [OSERDESE2]
└─── sdram (LiteDRAMCore)
│    └─── dfii (DFIInjector)
│    │    └─── pi0 (PhaseInjector)
│    │    └─── pi1 (PhaseInjector)
│    │    └─── pi2 (PhaseInjector)
│    │    └─── pi3 (PhaseInjector)
│    └─── controller (LiteDRAMController)
│    │    └─── refresher (Refresher)
│    │    │    └─── timer (RefreshTimer)
│    │    │    └─── postponer (RefreshPostponer)
│    │    │    └─── sequencer (RefreshSequencer)
│    │    │    │    └─── refreshexecuter_0* (RefreshExecuter)
│    │    │    └─── zqcs_timer (RefreshTimer)
│    │    │    └─── zqs_executer (ZQCSExecuter)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_0* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_1* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_2* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_3* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_4* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_5* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_6* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── bankmachine_7* (BankMachine)
│    │    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    │    └─── buffer_0* (Buffer)
│    │    │    │    └─── pipe_valid (PipeValid)
│    │    │    │    └─── pipeline (Pipeline)
│    │    │    └─── twtpcon (tXXDController)
│    │    │    └─── trccon (tXXDController)
│    │    │    └─── trascon (tXXDController)
│    │    │    └─── fsm (FSM)
│    │    └─── multiplexer (Multiplexer)
│    │    │    └─── choose_cmd (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── choose_req (_CommandChooser)
│    │    │    │    └─── roundrobin_0* (RoundRobin)
│    │    │    └─── _steerer_0* (_Steerer)
│    │    │    └─── trrdcon (tXXDController)
│    │    │    └─── tfawcon (tFAWController)
│    │    │    └─── tccdcon (tXXDController)
│    │    │    └─── twtrcon (tXXDController)
│    │    │    └─── fsm (FSM)
│    └─── crossbar (LiteDRAMCrossbar)
│    │    └─── roundrobin_0* (RoundRobin)
│    │    └─── roundrobin_1* (RoundRobin)
│    │    └─── roundrobin_2* (RoundRobin)
│    │    └─── roundrobin_3* (RoundRobin)
│    │    └─── roundrobin_4* (RoundRobin)
│    │    └─── roundrobin_5* (RoundRobin)
│    │    └─── roundrobin_6* (RoundRobin)
│    │    └─── roundrobin_7* (RoundRobin)
└─── litedramaxi2native_0* (LiteDRAMAXI2Native)
│    └─── write (LiteDRAMAXI2NativeW)
│    │    └─── buffer_0* (Buffer)
│    │    │    └─── pipe_valid (PipeValid)
│    │    │    └─── pipeline (Pipeline)
│    │    └─── aw_burst2beat (AXIBurst2Beat)
│    │    └─── w_buffer (SyncFIFO)
│    │    │    └─── fifo (SyncFIFOBuffered)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    └─── fifo (SyncFIFO)
│    │    └─── syncfifo_1* (SyncFIFO)
│    │    │    └─── fifo (SyncFIFO)
│    └─── read (LiteDRAMAXI2NativeR)
│    │    └─── buffer_0* (Buffer)
│    │    │    └─── pipe_valid (PipeValid)
│    │    │    └─── pipeline (Pipeline)
│    │    └─── ar_burst2beat (AXIBurst2Beat)
│    │    └─── r_buffer (SyncFIFO)
│    │    │    └─── fifo (SyncFIFOBuffered)
│    │    │    │    └─── fifo (SyncFIFO)
│    │    └─── syncfifo_0* (SyncFIFO)
│    │    │    └─── fifo (SyncFIFO)
│    └─── roundrobin_0* (RoundRobin)
└─── l2_cache (Cache)
│    └─── fsm (FSM)
└─── wishbone_bridge (LiteDRAMWishbone2Native)
│    └─── fsm (FSM)
└─── leds (LedChaser)
│    └─── waittimer_0* (WaitTimer)
└─── csr_bridge (Wishbone2CSR)
│    └─── fsm (FSM)
└─── csr_bankarray (CSRBankArray)
│    └─── csrbank_0* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    └─── csrbank_1* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstorage_4* (CSRStorage)
│    │    └─── csrstorage_5* (CSRStorage)
│    └─── sram_0* (SRAM)
│    └─── csrbank_2* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    └─── csrbank_3* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstorage_4* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstorage_5* (CSRStorage)
│    │    └─── csrstorage_6* (CSRStorage)
│    │    └─── csrstorage_7* (CSRStorage)
│    │    └─── csrstorage_8* (CSRStorage)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstorage_9* (CSRStorage)
│    │    └─── csrstorage_10* (CSRStorage)
│    │    └─── csrstorage_11* (CSRStorage)
│    │    └─── csrstorage_12* (CSRStorage)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstorage_13* (CSRStorage)
│    │    └─── csrstorage_14* (CSRStorage)
│    │    └─── csrstorage_15* (CSRStorage)
│    │    └─── csrstorage_16* (CSRStorage)
│    │    └─── csrstatus_3* (CSRStatus)
│    └─── csrbank_4* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstorage_4* (CSRStorage)
│    └─── csrbank_5* (CSRBank)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstatus_3* (CSRStatus)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstatus_4* (CSRStatus)
│    │    └─── csrstatus_5* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
* : Generated name.
[]: BlackBox.

INFO:SoC:--------------------------------------------------------------------------------
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libc'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libc'
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libcompiler_rt'
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libbase'
 CC       console.o
 CC       system.o
 CC       memtest.o
 CC       uart.o
 CC       spiflash.o
 CC       i2c.o
 CC       isr.o
 AR       libbase.a
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libbase'
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libfatfs'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libfatfs'
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/liblitespi'
 CC       spiflash.o
 AR       liblitespi.a
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/liblitespi'
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/liblitedram'
 CC       sdram.o
 CC       bist.o
 CC       sdram_dbg.o
 CC       sdram_spd.o
 CC       utils.o
 CC       accessors.o
 AR       liblitedram.a
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/liblitedram'
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libliteeth'
 CC       udp.o
 CC       mdio.o
 AR       libliteeth.a
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/libliteeth'
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/liblitesdcard'
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/liblitesdcard'
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/liblitesata'
 CC       sata.o
 AR       liblitesata.a
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/liblitesata'
make: Entering directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/bios'
 CC       boot.o
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       cmd_litesata.o
 CC       sim_debug.o
 CC       main.o
 CC       crt0.o
 CC       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.crcfbigen bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/bios/../include/generated/regions.ld riscv64-unknown-elf

ROM usage: 27.76KiB     (21.69%)
RAM usage: 1.38KiB  (17.29%)

rm crt0.o
make: Leaving directory '/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x6f2c).
INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x6f2c.

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source digilent_arty.tcl
# create_project -force -name digilent_arty -part xc7a100tcsg324-1
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1323.246 ; gain = 0.023 ; free physical = 2794 ; free virtual = 31648
# set_msg_config -id {Common 17-55} -new_severity {Warning}
# read_verilog {/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/Ram_1w_1rs_Generic.v}
# read_verilog {/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v}
# read_verilog {/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v}
# read_xdc digilent_arty.xdc
# set_property PROCESSING_ORDER EARLY [get_files digilent_arty.xdc]
# synth_design -directive default -top digilent_arty -part xc7a100tcsg324-1
Command: synth_design -directive default -top digilent_arty -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 320055
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2059.031 ; gain = 403.715 ; free physical = 1796 ; free virtual = 30650
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'digilent_arty' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:21]
INFO: [Synth 8-3876] $readmem data file 'digilent_arty_rom.init' is read successfully [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12627]
INFO: [Synth 8-3876] $readmem data file 'digilent_arty_sram.init' is read successfully [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12642]
INFO: [Synth 8-3876] $readmem data file 'digilent_arty_mem.init' is read successfully [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12665]
INFO: [Synth 8-155] case statement is not full and has no default [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:11812]
INFO: [Synth 8-155] case statement is not full and has no default [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:11835]
INFO: [Synth 8-155] case statement is not full and has no default [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:11904]
INFO: [Synth 8-155] case statement is not full and has no default [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:11916]
INFO: [Synth 8-155] case statement is not full and has no default [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12068]
INFO: [Synth 8-155] case statement is not full and has no default [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12123]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12616]
INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:75727]
INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:75727]
WARNING: [Synth 8-7071] port 'RDY' of module 'IDELAYCTRL' is unconnected for instance 'IDELAYCTRL' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12616]
WARNING: [Synth 8-7023] instance 'IDELAYCTRL' of module 'IDELAYCTRL' has 3 connections declared, but only 2 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12616]
INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:97310]
    Parameter DATA_RATE_OQ bound to: DDR - type: string 
    Parameter DATA_RATE_TQ bound to: BUF - type: string 
    Parameter DATA_WIDTH bound to: 8 - type: integer 
    Parameter SERDES_MODE bound to: MASTER - type: string 
    Parameter TRISTATE_WIDTH bound to: 1 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:97310]
WARNING: [Synth 8-7071] port 'OFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'SHIFTOUT1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'SHIFTOUT2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'TBYTEOUT' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'TFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'TQ' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'SHIFTIN1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'SHIFTIN2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'T1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'T2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'T3' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'T4' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'TBYTEIN' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7071] port 'TCE' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
WARNING: [Synth 8-7023] instance 'OSERDESE2' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12722]
INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:93073]
INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:93073]
WARNING: [Synth 8-7071] port 'OFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'SHIFTOUT1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'SHIFTOUT2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'TBYTEOUT' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'TFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'TQ' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'SHIFTIN1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'SHIFTIN2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'T1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'T2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'T3' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'T4' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'TBYTEIN' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'TCE' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_1' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7023] instance 'OSERDESE2_1' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12750]
WARNING: [Synth 8-7071] port 'OFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'SHIFTOUT1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'SHIFTOUT2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'TBYTEOUT' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'TFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'TQ' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'SHIFTIN1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'SHIFTIN2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'T1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'T2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'T3' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'T4' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'TBYTEIN' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'TCE' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_2' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7023] instance 'OSERDESE2_2' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12772]
WARNING: [Synth 8-7071] port 'OFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'SHIFTOUT1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'SHIFTOUT2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'TBYTEOUT' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'TFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'TQ' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'SHIFTIN1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'SHIFTIN2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'T1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'T2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'T3' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'T4' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'TBYTEIN' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'TCE' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_3' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7023] instance 'OSERDESE2_3' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12794]
WARNING: [Synth 8-7071] port 'OFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'SHIFTOUT1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'SHIFTOUT2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'TBYTEOUT' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'TFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'TQ' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'SHIFTIN1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'SHIFTIN2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'T1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'T2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'T3' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'T4' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'TBYTEIN' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'TCE' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_4' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7023] instance 'OSERDESE2_4' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12816]
WARNING: [Synth 8-7071] port 'OFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'SHIFTOUT1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'SHIFTOUT2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'TBYTEOUT' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'TFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'TQ' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'SHIFTIN1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'SHIFTIN2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'T1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'T2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'T3' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'T4' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'TBYTEIN' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'TCE' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_5' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7023] instance 'OSERDESE2_5' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12838]
WARNING: [Synth 8-7071] port 'OFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'SHIFTOUT1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'SHIFTOUT2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'TBYTEOUT' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'TFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'TQ' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'SHIFTIN1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'SHIFTIN2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'T1' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'T2' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'T3' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'T4' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'TBYTEIN' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'TCE' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_6' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7023] instance 'OSERDESE2_6' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12860]
WARNING: [Synth 8-7071] port 'OFB' of module 'OSERDESE2' is unconnected for instance 'OSERDESE2_7' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12882]
INFO: [Common 17-14] Message 'Synth 8-7071' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-7023] instance 'OSERDESE2_7' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12882]
WARNING: [Synth 8-7023] instance 'OSERDESE2_8' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12904]
WARNING: [Synth 8-7023] instance 'OSERDESE2_9' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12926]
WARNING: [Synth 8-7023] instance 'OSERDESE2_10' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12948]
WARNING: [Synth 8-7023] instance 'OSERDESE2_11' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12970]
WARNING: [Synth 8-7023] instance 'OSERDESE2_12' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:12992]
WARNING: [Synth 8-7023] instance 'OSERDESE2_13' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13014]
WARNING: [Synth 8-7023] instance 'OSERDESE2_14' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13036]
WARNING: [Synth 8-7023] instance 'OSERDESE2_15' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13058]
WARNING: [Synth 8-7023] instance 'OSERDESE2_16' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13080]
WARNING: [Synth 8-7023] instance 'OSERDESE2_17' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13102]
WARNING: [Synth 8-7023] instance 'OSERDESE2_18' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13124]
WARNING: [Synth 8-7023] instance 'OSERDESE2_19' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13146]
WARNING: [Synth 8-7023] instance 'OSERDESE2_20' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13168]
WARNING: [Synth 8-7023] instance 'OSERDESE2_21' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13190]
WARNING: [Synth 8-7023] instance 'OSERDESE2_22' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13212]
WARNING: [Synth 8-7023] instance 'OSERDESE2_23' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13234]
WARNING: [Synth 8-7023] instance 'OSERDESE2_24' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13256]
WARNING: [Synth 8-7023] instance 'OSERDESE2_25' of module 'OSERDESE2' has 27 connections declared, but only 17 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13278]
INFO: [Synth 8-6157] synthesizing module 'IOBUFDS' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78214]
INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78214]
WARNING: [Synth 8-7023] instance 'IOBUFDS' of module 'IOBUFDS' has 5 connections declared, but only 4 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13298]
WARNING: [Synth 8-7023] instance 'OSERDESE2_26' of module 'OSERDESE2' has 27 connections declared, but only 17 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13311]
WARNING: [Synth 8-7023] instance 'IOBUFDS_1' of module 'IOBUFDS' has 5 connections declared, but only 4 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13331]
WARNING: [Synth 8-7023] instance 'OSERDESE2_27' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13344]
WARNING: [Synth 8-7023] instance 'OSERDESE2_28' of module 'OSERDESE2' has 27 connections declared, but only 13 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13366]
WARNING: [Synth 8-7023] instance 'OSERDESE2_29' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13388]
INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:80759]
    Parameter DATA_RATE bound to: DDR - type: string 
    Parameter DATA_WIDTH bound to: 8 - type: integer 
    Parameter INTERFACE_TYPE bound to: NETWORKING - type: string 
    Parameter IOBDELAY bound to: IFD - type: string 
    Parameter NUM_CE bound to: 1 - type: integer 
    Parameter SERDES_MODE bound to: MASTER - type: string 
INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:80759]
WARNING: [Synth 8-7023] instance 'ISERDESE2' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13414]
INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:75740]
    Parameter CINVCTRL_SEL bound to: FALSE - type: string 
    Parameter DELAY_SRC bound to: IDATAIN - type: string 
    Parameter HIGH_PERFORMANCE_MODE bound to: TRUE - type: string 
    Parameter IDELAY_TYPE bound to: VARIABLE - type: string 
    Parameter IDELAY_VALUE bound to: 0 - type: integer 
    Parameter PIPE_SEL bound to: FALSE - type: string 
    Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: double 
    Parameter SIGNAL_PATTERN bound to: DATA - type: string 
INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:75740]
WARNING: [Synth 8-7023] instance 'IDELAYE2' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13441]
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
WARNING: [Synth 8-7023] instance 'OSERDESE2_30' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13464]
WARNING: [Synth 8-7023] instance 'ISERDESE2_1' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13490]
WARNING: [Synth 8-7023] instance 'IDELAYE2_1' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13517]
WARNING: [Synth 8-7023] instance 'OSERDESE2_31' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13540]
WARNING: [Synth 8-7023] instance 'ISERDESE2_2' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13566]
WARNING: [Synth 8-7023] instance 'IDELAYE2_2' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13593]
WARNING: [Synth 8-7023] instance 'OSERDESE2_32' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13616]
WARNING: [Synth 8-7023] instance 'ISERDESE2_3' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13642]
WARNING: [Synth 8-7023] instance 'IDELAYE2_3' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13669]
WARNING: [Synth 8-7023] instance 'OSERDESE2_33' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13692]
WARNING: [Synth 8-7023] instance 'ISERDESE2_4' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13718]
WARNING: [Synth 8-7023] instance 'IDELAYE2_4' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13745]
WARNING: [Synth 8-7023] instance 'OSERDESE2_34' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13768]
WARNING: [Synth 8-7023] instance 'ISERDESE2_5' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13794]
WARNING: [Synth 8-7023] instance 'IDELAYE2_5' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13821]
WARNING: [Synth 8-7023] instance 'OSERDESE2_35' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13844]
WARNING: [Synth 8-7023] instance 'ISERDESE2_6' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13870]
WARNING: [Synth 8-7023] instance 'IDELAYE2_6' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13897]
WARNING: [Synth 8-7023] instance 'OSERDESE2_36' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13920]
WARNING: [Synth 8-7023] instance 'ISERDESE2_7' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13946]
WARNING: [Synth 8-7023] instance 'IDELAYE2_7' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13973]
WARNING: [Synth 8-7023] instance 'OSERDESE2_37' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:13996]
WARNING: [Synth 8-7023] instance 'ISERDESE2_8' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14022]
WARNING: [Synth 8-7023] instance 'IDELAYE2_8' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14049]
WARNING: [Synth 8-7023] instance 'OSERDESE2_38' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14072]
WARNING: [Synth 8-7023] instance 'ISERDESE2_9' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14098]
WARNING: [Synth 8-7023] instance 'IDELAYE2_9' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14125]
WARNING: [Synth 8-7023] instance 'OSERDESE2_39' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14148]
WARNING: [Synth 8-7023] instance 'ISERDESE2_10' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14174]
WARNING: [Synth 8-7023] instance 'IDELAYE2_10' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14201]
WARNING: [Synth 8-7023] instance 'OSERDESE2_40' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14224]
WARNING: [Synth 8-7023] instance 'ISERDESE2_11' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14250]
WARNING: [Synth 8-7023] instance 'IDELAYE2_11' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14277]
WARNING: [Synth 8-7023] instance 'OSERDESE2_41' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14300]
WARNING: [Synth 8-7023] instance 'ISERDESE2_12' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14326]
WARNING: [Synth 8-7023] instance 'IDELAYE2_12' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14353]
WARNING: [Synth 8-7023] instance 'OSERDESE2_42' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14376]
WARNING: [Synth 8-7023] instance 'ISERDESE2_13' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14402]
WARNING: [Synth 8-7023] instance 'IDELAYE2_13' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14429]
WARNING: [Synth 8-7023] instance 'OSERDESE2_43' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14452]
WARNING: [Synth 8-7023] instance 'ISERDESE2_14' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14478]
WARNING: [Synth 8-7023] instance 'IDELAYE2_14' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14505]
WARNING: [Synth 8-7023] instance 'OSERDESE2_44' of module 'OSERDESE2' has 27 connections declared, but only 16 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14528]
WARNING: [Synth 8-7023] instance 'ISERDESE2_15' of module 'ISERDESE2' has 28 connections declared, but only 15 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14554]
WARNING: [Synth 8-7023] instance 'IDELAYE2_15' of module 'IDELAYE2' has 12 connections declared, but only 7 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14581]
INFO: [Synth 8-6157] synthesizing module 'FDCE' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:40789]
INFO: [Synth 8-6155] done synthesizing module 'FDCE' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:40789]
INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351]
    Parameter CLKFBOUT_MULT bound to: 16 - type: integer 
    Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double 
    Parameter CLKOUT0_DIVIDE bound to: 16 - type: integer 
    Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double 
    Parameter CLKOUT1_DIVIDE bound to: 64 - type: integer 
    Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double 
    Parameter CLKOUT2_DIVIDE bound to: 4 - type: integer 
    Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double 
    Parameter CLKOUT3_DIVIDE bound to: 4 - type: integer 
    Parameter CLKOUT3_PHASE bound to: 90.000000 - type: double 
    Parameter CLKOUT4_DIVIDE bound to: 8 - type: integer 
    Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double 
    Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
    Parameter REF_JITTER1 bound to: 0.010000 - type: double 
    Parameter STARTUP_WAIT bound to: FALSE - type: string 
INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351]
WARNING: [Synth 8-7023] instance 'PLLE2_ADV' of module 'PLLE2_ADV' has 21 connections declared, but only 11 given [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14932]
INFO: [Synth 8-6157] synthesizing module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:7]
INFO: [Synth 8-6157] synthesizing module 'BufferCC' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66164]
INFO: [Synth 8-6155] done synthesizing module 'BufferCC' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66164]
INFO: [Synth 8-6157] synthesizing module 'BufferCC_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66140]
INFO: [Synth 8-6155] done synthesizing module 'BufferCC_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66140]
INFO: [Synth 8-6157] synthesizing module 'NaxRiscv' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:22032]
INFO: [Synth 8-6157] synthesizing module 'TranslatorWithRollback' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:76848]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor_13' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:78447]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor_13' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:78447]
INFO: [Synth 8-6155] done synthesizing module 'TranslatorWithRollback' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:76848]
INFO: [Synth 8-6157] synthesizing module 'AllocatorMultiPortMem' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:76648]
INFO: [Synth 8-6155] done synthesizing module 'AllocatorMultiPortMem' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:76648]
INFO: [Synth 8-6157] synthesizing module 'DataCache' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:72974]
INFO: [Synth 8-6157] synthesizing module 'Ram_1w_1rs' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/Ram_1w_1rs_Generic.v:2]
    Parameter wordCount bound to: 512 - type: integer 
    Parameter wordWidth bound to: 64 - type: integer 
    Parameter clockCrossing bound to: 1'b0 
    Parameter technology bound to: auto - type: string 
    Parameter readUnderWrite bound to: dontCare - type: string 
    Parameter wrAddressWidth bound to: 9 - type: integer 
    Parameter wrDataWidth bound to: 64 - type: integer 
    Parameter wrMaskWidth bound to: 8 - type: integer 
    Parameter wrMaskEnable bound to: 1'b1 
    Parameter rdAddressWidth bound to: 9 - type: integer 
    Parameter rdDataWidth bound to: 64 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Ram_1w_1rs' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/Ram_1w_1rs_Generic.v:2]
INFO: [Synth 8-6155] done synthesizing module 'DataCache' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:72974]
INFO: [Synth 8-6157] synthesizing module 'StreamFifoLowLatency' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:72927]
INFO: [Synth 8-6157] synthesizing module 'StreamFifo_4' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:78326]
INFO: [Synth 8-6155] done synthesizing module 'StreamFifo_4' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:78326]
INFO: [Synth 8-6155] done synthesizing module 'StreamFifoLowLatency' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:72927]
INFO: [Synth 8-6157] synthesizing module 'DivRadix4' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:72744]
INFO: [Synth 8-6155] done synthesizing module 'DivRadix4' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:72744]
INFO: [Synth 8-6157] synthesizing module 'PrefetchPredictor' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:72727]
INFO: [Synth 8-6155] done synthesizing module 'PrefetchPredictor' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:72727]
INFO: [Synth 8-6157] synthesizing module 'IssueQueue' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:70349]
INFO: [Synth 8-6155] done synthesizing module 'IssueQueue' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:70349]
INFO: [Synth 8-6157] synthesizing module 'RegFileAsync' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69998]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwMux_3' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:78049]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor_15' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:78572]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor_15' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:78572]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwMux_3' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:78049]
INFO: [Synth 8-6155] done synthesizing module 'RegFileAsync' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69998]
INFO: [Synth 8-6157] synthesizing module 'DependencyStorage' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69825]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor_11' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:77952]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor_11' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:77952]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor_12' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:77471]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor_12' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:77471]
INFO: [Synth 8-6155] done synthesizing module 'DependencyStorage' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69825]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwMux' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69734]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor_10' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:77402]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor_10' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:77402]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwMux' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69734]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwMux_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69667]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor_9' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:77347]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor_9' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:77347]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwMux_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69667]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69570]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69570]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69483]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69483]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor_6' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69420]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor_6' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69420]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwMux_2' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69353]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwMux_2' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69353]
INFO: [Synth 8-6157] synthesizing module 'RamAsyncMwXor_7' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69270]
INFO: [Synth 8-6155] done synthesizing module 'RamAsyncMwXor_7' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69270]
INFO: [Synth 8-6155] done synthesizing module 'NaxRiscv' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:22032]
INFO: [Synth 8-6157] synthesizing module 'WidthAdapter' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:21769]
INFO: [Synth 8-6155] done synthesizing module 'WidthAdapter' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:21769]
INFO: [Synth 8-6157] synthesizing module 'Arbiter' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:21413]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_12' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69086]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_12' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69086]
INFO: [Synth 8-6155] done synthesizing module 'Arbiter' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:21413]
INFO: [Synth 8-6157] synthesizing module 'Axi4Bridge' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:20706]
INFO: [Synth 8-6157] synthesizing module 'ContextAsyncBufferFull_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69038]
INFO: [Synth 8-6155] done synthesizing module 'ContextAsyncBufferFull_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:69038]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_11' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68954]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_11' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68954]
INFO: [Synth 8-6155] done synthesizing module 'Axi4Bridge' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:20706]
INFO: [Synth 8-6157] synthesizing module 'Decoder' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:20338]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_10' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68774]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_10' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68774]
INFO: [Synth 8-6155] done synthesizing module 'Decoder' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:20338]
INFO: [Synth 8-6157] synthesizing module 'WidthAdapter_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:19980]
INFO: [Synth 8-6157] synthesizing module 'ContextAsyncBufferFull' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68726]
INFO: [Synth 8-6155] done synthesizing module 'ContextAsyncBufferFull' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68726]
INFO: [Synth 8-6155] done synthesizing module 'WidthAdapter_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:19980]
INFO: [Synth 8-6157] synthesizing module 'WidthAdapter_2' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:19703]
INFO: [Synth 8-6155] done synthesizing module 'WidthAdapter_2' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:19703]
INFO: [Synth 8-6157] synthesizing module 'TransferFilter' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:19288]
INFO: [Synth 8-6155] done synthesizing module 'TransferFilter' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:19288]
INFO: [Synth 8-6157] synthesizing module 'TilelinkClint' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:18915]
INFO: [Synth 8-6155] done synthesizing module 'TilelinkClint' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:18915]
INFO: [Synth 8-6157] synthesizing module 'TilelinkPlic' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:16332]
INFO: [Synth 8-6155] done synthesizing module 'TilelinkPlic' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:16332]
INFO: [Synth 8-6157] synthesizing module 'AxiLite4Bridge' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:15818]
INFO: [Synth 8-6155] done synthesizing module 'AxiLite4Bridge' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:15818]
INFO: [Synth 8-6157] synthesizing module 'Decoder_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:15323]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_9' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68475]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_9' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68475]
INFO: [Synth 8-6155] done synthesizing module 'Decoder_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:15323]
INFO: [Synth 8-6157] synthesizing module 'Cache' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:7836]
INFO: [Synth 8-6157] synthesizing module 'StreamDemux' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68438]
INFO: [Synth 8-6155] done synthesizing module 'StreamDemux' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68438]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_4' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68375]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_4' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68375]
INFO: [Synth 8-6157] synthesizing module 'StreamFifo_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68221]
INFO: [Synth 8-6155] done synthesizing module 'StreamFifo_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:68221]
INFO: [Synth 8-6157] synthesizing module 'StreamFifo_2' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:67792]
INFO: [Synth 8-6155] done synthesizing module 'StreamFifo_2' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:67792]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_5' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:67543]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_5' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:67543]
INFO: [Synth 8-6157] synthesizing module 'StreamFifo_3' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:67186]
INFO: [Synth 8-6155] done synthesizing module 'StreamFifo_3' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:67186]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_6' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:67013]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_6' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:67013]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_7' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66836]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_7' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66836]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_8' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66540]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_8' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66540]
INFO: [Synth 8-6157] synthesizing module 'Ram_1w_1rs__parameterized0' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/Ram_1w_1rs_Generic.v:2]
    Parameter wordCount bound to: 8 - type: integer 
    Parameter wordWidth bound to: 216 - type: integer 
    Parameter clockCrossing bound to: 1'b0 
    Parameter technology bound to: auto - type: string 
    Parameter readUnderWrite bound to: dontCare - type: string 
    Parameter wrAddressWidth bound to: 3 - type: integer 
    Parameter wrDataWidth bound to: 216 - type: integer 
    Parameter wrMaskWidth bound to: 8 - type: integer 
    Parameter wrMaskEnable bound to: 1'b1 
    Parameter rdAddressWidth bound to: 3 - type: integer 
    Parameter rdDataWidth bound to: 216 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Ram_1w_1rs__parameterized0' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/Ram_1w_1rs_Generic.v:2]
INFO: [Synth 8-6155] done synthesizing module 'Cache' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:7836]
INFO: [Synth 8-6157] synthesizing module 'Arbiter_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:7298]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66391]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66391]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_2' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66247]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_2' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66247]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter_3' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66188]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter_3' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:66188]
INFO: [Synth 8-6155] done synthesizing module 'Arbiter_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:7298]
INFO: [Synth 8-6157] synthesizing module 'TransferFilter_1' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:6760]
INFO: [Synth 8-6155] done synthesizing module 'TransferFilter_1' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:6760]
INFO: [Synth 8-6157] synthesizing module 'StreamFifo' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:6560]
INFO: [Synth 8-6155] done synthesizing module 'StreamFifo' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:6560]
INFO: [Synth 8-6157] synthesizing module 'StreamArbiter' [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:6385]
INFO: [Synth 8-6155] done synthesizing module 'StreamArbiter' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:6385]
INFO: [Synth 8-6155] done synthesizing module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' (0#1) [/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:7]
ERROR: [Synth 8-11365] for the instance 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' declared at '/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:7', named port connection 'clk' does not exist [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14947]
WARNING: [Synth 8-689] width (8) of port connection 'mBus_bid' does not match port width (4) of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14950]
WARNING: [Synth 8-689] width (8) of port connection 'mBus_rid' does not match port width (4) of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14954]
ERROR: [Synth 8-11365] for the instance 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' declared at '/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009.v:7', named port connection 'reset' does not exist [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14968]
WARNING: [Synth 8-689] width (32) of port connection 'mBus_araddr' does not match port width (28) of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14969]
WARNING: [Synth 8-689] width (8) of port connection 'mBus_arid' does not match port width (4) of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14971]
WARNING: [Synth 8-689] width (32) of port connection 'mBus_awaddr' does not match port width (28) of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14975]
WARNING: [Synth 8-689] width (8) of port connection 'mBus_awid' does not match port width (4) of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14978]
WARNING: [Synth 8-689] width (1) of port connection 'pBus_arprot' does not match port width (3) of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14989]
WARNING: [Synth 8-689] width (1) of port connection 'pBus_awprot' does not match port width (3) of module 'NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:14992]
INFO: [Synth 8-6157] synthesizing module 'FDPE' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:40945]
    Parameter INIT bound to: 1'b1 
ERROR: [Synth 8-6156] failed synthesizing module 'FDPE' [/opt/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:40945]
ERROR: [Synth 8-6156] failed synthesizing module 'digilent_arty' [/home/hsubedi/instruction_test_bed/litex/fpga_nax_3/build/digilent_arty/gateware/digilent_arty.v:21]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2235.969 ; gain = 580.652 ; free physical = 1603 ; free virtual = 30456
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
166 Infos, 190 Warnings, 0 Critical Warnings and 5 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Fri Oct 27 16:46:53 2023...
Traceback (most recent call last):
  File "/usr/lib/python3.10/runpy.py", line 196, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "/usr/lib/python3.10/runpy.py", line 86, in _run_code
    exec(code, run_globals)
  File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex-boards/litex_boards/targets/digilent_arty.py", line 214, in <module>
    main()
  File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex-boards/litex_boards/targets/digilent_arty.py", line 203, in main
    builder.build(**parser.toolchain_argdict)
  File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/soc/integration/builder.py", line 367, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/soc/integration/soc.py", line 1364, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/build/xilinx/platform.py", line 97, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/build/xilinx/vivado.py", line 141, in build
    return GenericToolchain.build(self, platform, fragment, **kwargs)
  File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/build/generic_toolchain.py", line 123, in build
    self.run_script(script)
  File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/build/xilinx/vivado.py", line 401, in run_script
    raise OSError("Error occured during Vivado's script execution.")
OSError: Error occured during Vivado's script execution.
hsubedi@kronos:~/instruction_test_bed/litex/fpga_nax_3$

full error is here

di@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull$ git clone --recursive https://github.com/SpinalHDL/NaxRiscv.git
Cloning into 'NaxRiscv'...
remote: Enumerating objects: 10689, done.
remote: Counting objects: 100% (1634/1634), done.
remote: Compressing objects: 100% (753/753), done.
remote: Total 10689 (delta 835), reused 1557 (delta 765), pack-reused 9055
Receiving objects: 100% (10689/10689), 3.68 MiB | 4.80 MiB/s, done.
Resolving deltas: 100% (5593/5593), done.
Submodule 'ext/NaxSoftware' (https://github.com/SpinalHDL/NaxSoftware.git) registered for path 'ext/NaxSoftware'
Submodule 'ext/SpinalHDL' (https://github.com/SpinalHDL/SpinalHDL.git) registered for path 'ext/SpinalHDL'
Submodule 'ext/riscv-isa-sim' (https://github.com/SpinalHDL/riscv-isa-sim.git) registered for path 'ext/riscv-isa-sim'
Submodule 'ext/rvls' (https://github.com/SpinalHDL/rvls.git) registered for path 'ext/rvls'
Cloning into '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/NaxSoftware'...
remote: Enumerating objects: 2547, done.        
remote: Counting objects: 100% (188/188), done.        
remote: Compressing objects: 100% (115/115), done.        
remote: Total 2547 (delta 79), reused 141 (delta 41), pack-reused 2359        
Receiving objects: 100% (2547/2547), 15.64 MiB | 4.44 MiB/s, done.
Resolving deltas: 100% (1400/1400), done.
Cloning into '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL'...
remote: Enumerating objects: 97467, done.        
remote: Counting objects: 100% (17185/17185), done.        
remote: Compressing objects: 100% (3280/3280), done.        
remote: Total 97467 (delta 15716), reused 14541 (delta 13580), pack-reused 80282        
Receiving objects: 100% (97467/97467), 38.21 MiB | 10.95 MiB/s, done.
Resolving deltas: 100% (45878/45878), done.
Cloning into '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim'...
remote: Enumerating objects: 15867, done.        
remote: Counting objects: 100% (15867/15867), done.        
remote: Compressing objects: 100% (5085/5085), done.        
remote: Total 15867 (delta 9933), reused 15692 (delta 9840), pack-reused 0        
Receiving objects: 100% (15867/15867), 4.12 MiB | 10.64 MiB/s, done.
Resolving deltas: 100% (9933/9933), done.
Cloning into '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/rvls'...
remote: Enumerating objects: 191, done.        
remote: Counting objects: 100% (191/191), done.        
remote: Compressing objects: 100% (122/122), done.        
remote: Total 191 (delta 98), reused 139 (delta 49), pack-reused 0        
Receiving objects: 100% (191/191), 115.50 KiB | 4.81 MiB/s, done.
Resolving deltas: 100% (98/98), done.
Submodule path 'ext/NaxSoftware': checked out '8927ab57bb5b7f531d1c58fe96417bae2a264144'
Submodule path 'ext/SpinalHDL': checked out 'd82d8b51756bd5aeb4487af54c29c980707118d0'
Submodule 'tester/src/test/python/cocotblib' (https://github.com/SpinalHDL/CocotbLib.git) registered for path 'ext/SpinalHDL/tester/src/test/python/cocotblib'
Cloning into '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/tester/src/test/python/cocotblib'...
remote: Enumerating objects: 124, done.        
remote: Counting objects: 100% (56/56), done.        
remote: Compressing objects: 100% (13/13), done.        
remote: Total 124 (delta 45), reused 43 (delta 43), pack-reused 68        
Receiving objects: 100% (124/124), 30.72 KiB | 7.68 MiB/s, done.
Resolving deltas: 100% (68/68), done.
Submodule path 'ext/SpinalHDL/tester/src/test/python/cocotblib': checked out 'a98830423924fc89bfebae84cb802fc90d352602'
Submodule path 'ext/riscv-isa-sim': checked out '020ad5ac424c3c1ba4ed8e77458e2fec084b8cf6'
Submodule path 'ext/rvls': checked out 'd7e8d845077ff2f8be723b7d89acdeeda0d173b8'
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull$ l
dont_need_SpinalHDL/  NaxRiscv/  naxRiscv_recurisve/
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull$ cd NaxRiscv/
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv$ l
assets/  build.sbt  ext/  LICENSES/  project/  README.md  reuse.sh*  src/
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv$ sbt "runMain naxriscv.Gen64" && make -C src/test/cpp/naxriscv compile
[info] welcome to sbt 1.6.0 (Amazon.com Inc. Java 11.0.20.1)
[info] loading settings for project naxriscv-build from plugins.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/project
[info] compiling 1 Scala source to /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/project/target/scala-2.12/sbt-1.0/classes ...
[info] loading settings for project all from build.sbt ...
[info] set current project to NaxRiscv (in build file:/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/)
[info] compiling 2 Scala sources to /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/idslpayload/target/scala-2.11/classes ...
[info] compiling 16 Scala sources and 10 Java sources to /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/sim/target/scala-2.11/classes ...
[warn] there were three deprecation warnings; re-run with -deprecation for details
[warn] one warning found
[info] compiling 2 Scala sources to /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/idslplugin/target/scala-2.11/classes ...
[warn] there were 5 deprecation warnings; re-run with -deprecation for details
[warn] one warning found
[info] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/sim/src/main/java/spinal/sim/DynamicCompiler.java: DynamicCompiler.java uses or overrides a deprecated API.
[info] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/sim/src/main/java/spinal/sim/DynamicCompiler.java: Recompile with -Xlint:deprecation for details.
[info] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/sim/src/main/java/spinal/sim/DynamicCompiler.java: DynamicCompiler.java uses unchecked or unsafe operations.
[info] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/sim/src/main/java/spinal/sim/DynamicCompiler.java: Recompile with -Xlint:unchecked for details.
[info] compiling 67 Scala sources and 1 Java source to /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/core/target/scala-2.11/classes ...
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/core/src/main/scala/spinal/core/internals/Phase.scala:2601:25: non-variable type argument spinal.core.SpinalEnum in type pattern spinal.core.SpinalEnumCraft[spinal.core.SpinalEnum] is unchecked since it is eliminated by erasure
[warn]                 case d: SpinalEnumCraft[SpinalEnum] => d.init(d.spinalEnum.elements(0))
[warn]                         ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/core/src/main/scala/spinal/core/AFix.scala:232:5: match may not be exhaustive.
[warn] It would fail on the following input: SCRAP
[warn]     roundType match {
[warn]     ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/core/src/main/scala/spinal/core/Data.scala:361:29: match may not be exhaustive.
[warn] It would fail on the following inputs: inWithNull, outWithNull
[warn]   def dirString(): String = dir match {
[warn]                             ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/core/src/main/scala/spinal/core/Data.scala:535:16: match may not be exhaustive.
[warn] It would fail on the following inputs: inWithNull, outWithNull
[warn]           that.dir match {
[warn]                ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/core/src/main/scala/spinal/core/SInt.scala:390:5: match may not be exhaustive.
[warn] It would fail on the following input: SCRAP
[warn]     roundType match{
[warn]     ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/core/src/main/scala/spinal/core/UInt.scala:269:5: match may not be exhaustive.
[warn] It would fail on the following input: SCRAP
[warn]     roundType match{
[warn]     ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/core/src/main/scala/spinal/core/internals/Phase.scala:2487:12: match may not be exhaustive.
[warn] It would fail on the following inputs: inWithNull, inout, outWithNull
[warn]         io.dir match {
[warn]            ^
[warn] there were 13 deprecation warnings; re-run with -deprecation for details
[warn] there were four feature warnings; re-run with -feature for details
[warn] 9 warnings found
[info] compiling 441 Scala sources to /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/target/scala-2.11/classes ...
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/Stream.scala:755:14: abstract type T in type pattern spinal.lib.StreamArbiter[T] is unchecked since it is eliminated by erasure
[warn]     case c : StreamArbiter[T] => new Area {
[warn]              ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/bus/bmb/sim/BmbMemoryTester.scala:41:108: a pure expression does nothing in statement position; you may be omitting necessary parentheses
[warn]       override def regionFree(region: SizeMapping): Unit = if(checkAvailability) regions.free(region) else true
[warn]                                                                                                            ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/bus/tilelink/fabric/Axi4Bridge.scala:8:33: imported `Axi4Bridge' is permanently hidden by definition of class Axi4Bridge in package fabric
[warn] import spinal.lib.bus.tilelink.{Axi4Bridge, S2mSupport}
[warn]                                 ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/generator/ClockDomainGenerator.scala:272:5: a pure expression does nothing in statement position; you may be omitting necessary parentheses
[warn]     generator
[warn]     ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/Stream.scala:155:5: match may not be exhaustive.
[warn] It would fail on the following inputs: (false, true, true), (true, false, true), (true, true, true)
[warn]     (m2s, s2m, halfRate) match {
[warn]     ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/bus/fabric/MappedConnection.scala:38:13: match may not be exhaustive.
[warn] It would fail on the following input: Some((x: Any forSome x not in (BigInt, DefaultMapping)))
[warn]     mapping.automatic match {
[warn]             ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/bus/fabric/MappedUpDown.scala:67:19: match may not be exhaustive.
[warn] It would fail on the following input: Some((x: Any forSome x not in (BigInt, DefaultMapping, spinal.lib.bus.misc.AddressMapping)))
[warn]         c.mapping.automatic match {
[warn]                   ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/bus/regif/RegInst.scala:739:7: Exhaustivity analysis reached max recursion depth, not all missing cases are reported.
[warn] (Please try with scalac -Ypatmat-exhaust-depth 40 or -Ypatmat-exhaust-depth off.)
[warn]       accType match {
[warn]       ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/bus/regif/RegInst.scala:758:7: Exhaustivity analysis reached max recursion depth, not all missing cases are reported.
[warn] (Please try with scalac -Ypatmat-exhaust-depth 40 or -Ypatmat-exhaust-depth off.)
[warn]       accType match {
[warn]       ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/bus/tilelink/sim/Checker.scala:222:25: match may not be exhaustive.
[warn] It would fail on the following input: None
[warn]         inflightC.remove(d.source -> d.address) match {
[warn]                         ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/bus/tilelink/sim/Checker.scala:238:21: match may not be exhaustive.
[warn] It would fail on the following input: None
[warn]     inflightD.remove(e.sink) match {
[warn]                     ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/dsptool/FixData.scala:30:26: match may not be exhaustive.
[warn] It would fail on the following input: SCRAP
[warn]       val rounded = this.roundType match {
[warn]                          ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/pipeline/Pipeline.scala:167:22: match may not be exhaustive.
[warn] It would fail on the following input: Some((x: Any forSome x not in Pipeline.this.ConnectionModel))
[warn]       stageDriver.get(stage) match {
[warn]                      ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/system/dma/sg/MemoryCore.scala:112:7: match may not be exhaustive.
[warn] It would fail on the following input: (true, true)
[warn]       (p.writes(self).absolutePriority, p.writes(other).absolutePriority) match {
[warn]       ^
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/SpinalHDL/lib/src/main/scala/spinal/lib/system/dma/sg/MemoryCore.scala:198:7: match may not be exhaustive.
[warn] It would fail on the following input: (true, true)
[warn]       (p.reads(self).absolutePriority, p.reads(other).absolutePriority) match {
[warn]       ^
[warn] there were 82 deprecation warnings; re-run with -deprecation for details
[warn] there were 144 feature warnings; re-run with -feature for details
[warn] 17 warnings found
[info] compiling 125 Scala sources and 3 Java sources to /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/target/scala-2.11/classes ...
[warn] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/src/main/scala/naxriscv/platform/asic/test_a.scala:37:22: match may not be exhaustive.
[warn] It would fail on the following input: true
[warn]                   bb.wrMaskEnable match {
[warn]                      ^
[info] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/src/main/scala/naxriscv/sandbox/doc/Pres.scala:1:1: 
[info] Found names but no class, trait or object is defined in the compilation unit.
[info] The incremental compiler cannot record the dependency information in such case.
[info] Some errors like unused import referring to a non-existent class might not be reported.
[info]     
[info] // SPDX-FileCopyrightText: 2023 "Everybody"
[info] ^
[info] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/src/main/scala/naxriscv/sandbox/syntax/Spec.scala:1:1: 
[info] Found names but no class, trait or object is defined in the compilation unit.
[info] The incremental compiler cannot record the dependency information in such case.
[info] Some errors like unused import referring to a non-existent class might not be reported.
[info]     
[info] // SPDX-FileCopyrightText: 2023 "Everybody"
[info] ^
[info] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/src/main/scala/naxriscv/sandbox/doc/Pres.scala:1:1: 
[info] Found top level imports but no class, trait or object is defined in the compilation unit.
[info] The incremental compiler cannot record the dependency information in such case.
[info] Some errors like unused import referring to a non-existent class might not be reported.
[info]     
[info] // SPDX-FileCopyrightText: 2023 "Everybody"
[info] ^
[info] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/src/main/scala/naxriscv/sandbox/syntax/Spec.scala:1:1: 
[info] Found top level imports but no class, trait or object is defined in the compilation unit.
[info] The incremental compiler cannot record the dependency information in such case.
[info] Some errors like unused import referring to a non-existent class might not be reported.
[info]     
[info] // SPDX-FileCopyrightText: 2023 "Everybody"
[info] ^
[warn] there were 7 deprecation warnings; re-run with -deprecation for details
[warn] there were 74 feature warnings; re-run with -feature for details
[warn] three warnings found
[info] running (fork) naxriscv.Gen64 
[info] [Runtime] SpinalHDL dev    git head : d82d8b51756bd5aeb4487af54c29c980707118d0
[info] [Runtime] JVM max memory : 7960.0MiB
[info] [Runtime] Current date : 2023.10.27 17:40:00
[info] [Progress] at 0.000 : Elaborate components
[info] [Progress] at 2.247 : Checks and transforms
[info] [Progress] at 3.591 : Generate Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/CommitPlugin_logic_free_lineEventStream_fifo/fifo/logic_ram : Mem[32*8 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfAllocationPlugin_logic_allocator/ways_0_mem : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfAllocationPlugin_logic_allocator/ways_1_mem : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_0_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_0_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_1_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_1_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_2_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_2_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_3_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_3_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/status_mem : Mem[64*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/status_mem : Mem[64*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/ram_0 : Mem[16*41 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/ram_0 : Mem[16*41 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/ram_1 : Mem[16*41 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/ram_1 : Mem[16*41 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/ram_0 : Mem[16*81 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/ram_1 : Mem[16*81 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_lqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_lqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_lqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_lqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/ram_0 : Mem[16*29 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/ram_1 : Mem[16*29 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_ways_0_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_ways_1_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_ways_2_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_ways_3_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DecoderPredictionPlugin_logic_ras_mem_stack : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_addressPre : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_addressPre : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_physRd : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_physRd : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_robIdMsb : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_pc : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_writeRd : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_writeRd : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_lr : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_unsigned : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_unsigned : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_hazardPrediction_valid : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_hazardPrediction_delta : Mem[16*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_hazardPrediction_score : Mem[16*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_robIdMsb : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPre : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPre : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_amo : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_amo : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_sc : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_sc : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_data : Mem[16*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_data : Mem[16*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doNotBypass : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_0 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_1 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_2 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_3 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_1_ways_0 : Mem[32*31 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_1_ways_1 : Mem[32*31 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_0 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_1 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_2 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_3 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_1_ways_0 : Mem[32*31 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_1_ways_1 : Mem[32*31 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/CsrRamPlugin_logic_mem : Mem[16*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_target : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_DISPATCH_MASK_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_DISPATCH_MASK_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_0 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_0 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_0 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_0 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_1 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_1 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_1 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_1 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RD_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RD_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_ARCH_RD_banks_0 : Mem[32*10 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RD_FREE_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_SEL_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_HISTORY_banks_0 : Mem[32*24 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_HISTORY_banks_1 : Mem[32*24 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_DecoderPredictionPlugin_RAS_PUSH_PTR_banks_0 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_DecoderPredictionPlugin_RAS_PUSH_PTR_banks_1 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_LQ_ALLOC_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_SQ_ALLOC_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RS_0_banks_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RS_0_banks_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_0_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_0_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_0_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_0_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RS_1_banks_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RS_1_banks_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_1_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_1_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_1_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_1_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_ID_banks_0 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_ID_banks_1 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_LSU_ID_banks_0 : Mem[32*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_LSU_ID_banks_1 : Mem[32*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_ROB_MSB_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_ROB_MSB_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] 606 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 4.304
[info] [Runtime] SpinalHDL dev    git head : d82d8b51756bd5aeb4487af54c29c980707118d0
[info] [Runtime] JVM max memory : 7960.0MiB
[info] [Runtime] Current date : 2023.10.27 17:40:04
[info] [Progress] at 4.306 : Elaborate components
[info] [Progress] at 4.912 : Checks and transforms
[info] [Progress] at 5.707 : Generate Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_0 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_1 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_2 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/location/ram_3 : Mem[64*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/writes_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfTranslationPlugin_logic_impl/commits_ram/ram_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/CommitPlugin_logic_free_lineEventStream_fifo/fifo/logic_ram : Mem[32*8 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_0 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_1 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_2 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RegFilePlugin_logic_regfile/banks_0_ram/ram_3 : Mem[64*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_0 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob/ram_1 : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RfDependencyPlugin_logic_forRf_integer_impl/status_busy/ram_7 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/location/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/location/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfAllocationPlugin_logic_allocator/ways_0_mem : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/integer_RfAllocationPlugin_logic_allocator/ways_1_mem : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_0_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_0_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_1_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_1_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_2_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_2_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_3_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/ways_3_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/status_mem : Mem[64*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/status_mem : Mem[64*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DataCachePlugin_logic_cache/plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/ram_0 : Mem[16*41 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/ram_0 : Mem[16*41 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/ram_1 : Mem[16*41 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_earlyBranch/ram_1 : Mem[16*41 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/ram_0 : Mem[16*81 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_logic_mem_finalBranch/ram_1 : Mem[16*81 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_sqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_needTranslation/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_feededOnce/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_0 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_1 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doSpecial/ram_2 : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_lqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_lqAlloc/ram_0 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_lqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_lqAlloc/ram_1 : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/ram_0 : Mem[16*29 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/BranchContextPlugin_free_dispatchMem_mem/ram_1 : Mem[16*29 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0/ram_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_ways_0_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_ways_1_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_ways_2_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_ways_3_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_logic_plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/DecoderPredictionPlugin_logic_ras_mem_stack : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_addressPre : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_addressPre : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_physRd : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_physRd : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_robIdMsb : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_pc : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_writeRd : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_writeRd : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_lr : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_unsigned : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_unsigned : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_hazardPrediction_valid : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_hazardPrediction_delta : Mem[16*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_lq_mem_hazardPrediction_score : Mem[16*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_robIdMsb : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPre : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPre : Mem[16*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_amo : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_amo : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_sc : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_sc : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_data : Mem[16*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_data : Mem[16*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_logic_sq_mem_doNotBypass : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_0 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_1 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_2 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_3 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_1_ways_0 : Mem[32*31 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/FetchCachePlugin_setup_translationStorage_logic_sl_1_ways_1 : Mem[32*31 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_0 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_1 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_2 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_3 : Mem[32*49 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_1_ways_0 : Mem[32*31 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/Lsu2Plugin_setup_translationStorage_logic_sl_1_ways_1 : Mem[32*31 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/CsrRamPlugin_logic_mem : Mem[16*64 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_target : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_DISPATCH_MASK_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_DISPATCH_MASK_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_0 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_0 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_0 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_1 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_1 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PC_banks_1 : Mem[32*40 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RD_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RD_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_ARCH_RD_banks_0 : Mem[32*10 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RD_FREE_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_SEL_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_HISTORY_banks_0 : Mem[32*24 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_HISTORY_banks_1 : Mem[32*24 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_DecoderPredictionPlugin_RAS_PUSH_PTR_banks_0 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_DecoderPredictionPlugin_RAS_PUSH_PTR_banks_1 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_LQ_ALLOC_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_SQ_ALLOC_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RS_0_banks_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RS_0_banks_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_0_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_0_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_0_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_0_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RS_1_banks_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_PHYS_RS_1_banks_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_1_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_1_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_1_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_READ_RS_1_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_ID_banks_0 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_BRANCH_ID_banks_1 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_LSU_ID_banks_0 : Mem[32*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_LSU_ID_banks_1 : Mem[32*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_ROB_MSB_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/RobPlugin_logic_storage_ROB_MSB_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] 612 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 6.119
[success] Total time: 136 s (02:16), completed Oct 27, 2023, 5:40:06 PM
make: Entering directory '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/src/test/cpp/naxriscv'
verilator -cc  /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/NaxRiscv.v  -CFLAGS -std=c++14 -LDFLAGS -pthread  -CFLAGS -Iobj_dir -CFLAGS -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -CFLAGS -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -CFLAGS -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -CFLAGS -I -CFLAGS -lSDL2 -LDFLAGS -lSDL2 -CFLAGS -g -CFLAGS -rdynamic -O3  -CFLAGS -O3  -O3 -CFLAGS -DTRACE  --autoflush --output-split 5000 --output-split-cfuncs 500 --output-split-ctrace 500 --x-assign unique --gdbbt --trace-fst -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe src/main.cpp /libspike_main.a /libriscv.a /libdisasm.a /libsoftfloat.a /libfesvr.a /libfdt.a 
No stack.
cp /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/nax.h src/nax.h
make  -j -C obj_dir/ -f VNaxRiscv.mk VNaxRiscv LIBS="-lpthread -ldl -lboost_regex -lboost_system  -lpthread  -lboost_system -lboost_regex"
make[1]: Entering directory '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/src/test/cpp/naxriscv/obj_dir'
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o main.o ../src/main.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o verilated_dpi.o /usr/local/share/verilator/include/verilated_dpi.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o verilated_fst_c.o /usr/local/share/verilator/include/verilated_fst_c.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv.o VNaxRiscv.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv___024root__DepSet_h0b0b9331__0.o VNaxRiscv___024root__DepSet_h0b0b9331__0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv___024root__DepSet_h84750d36__0.o VNaxRiscv___024root__DepSet_h84750d36__0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__0.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__1.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__1.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__2.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__2.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__3.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__3.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__4.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__4.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__5.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__5.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__6.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__6.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__7.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__7.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__8.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__8.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__9.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__9.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__10.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__10.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__11.o VNaxRiscv_NaxRiscv__DepSet_h90299dc9__11.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__0.o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__1.o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__1.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__2.o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__2.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__3.o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__3.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__4.o VNaxRiscv_NaxRiscv__DepSet_h7aa9902c__4.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_RegFileAsync__DepSet_h607f4c30__0.o VNaxRiscv_RegFileAsync__DepSet_h607f4c30__0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_AllocatorMultiPortMem__DepSet_h72ab2242__0.o VNaxRiscv_AllocatorMultiPortMem__DepSet_h72ab2242__0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_AllocatorMultiPortMem__DepSet_hf12aaf01__0.o VNaxRiscv_AllocatorMultiPortMem__DepSet_hf12aaf01__0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv_RamAsyncMwMux_3__DepSet_heca73057__0.o VNaxRiscv_RamAsyncMwMux_3__DepSet_heca73057__0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv__Dpi.o VNaxRiscv__Dpi.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv__Trace__0.o VNaxRiscv__Trace__0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv__Trace__1.o VNaxRiscv__Trace__1.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv__Trace__2.o VNaxRiscv__Trace__2.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv__Trace__3.o VNaxRiscv__Trace__3.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv__Trace__4.o VNaxRiscv__Trace__4.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14 -Os -c -o VNaxRiscv__Trace__5.o VNaxRiscv__Trace__5.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_0.o VNaxRiscv__ConstPool_0.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_1.o VNaxRiscv__ConstPool_1.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_2.o VNaxRiscv__ConstPool_2.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_3.o VNaxRiscv__ConstPool_3.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_4.o VNaxRiscv__ConstPool_4.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_5.o VNaxRiscv__ConstPool_5.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_6.o VNaxRiscv__ConstPool_6.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_7.o VNaxRiscv__ConstPool_7.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_8.o VNaxRiscv__ConstPool_8.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_9.o VNaxRiscv__ConstPool_9.cpp
In file included from /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv/disasm.h:6,
                 from ../src/main.cpp:34:
/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv/decode.h:15:10: fatal error: config.h: No such file or directory
   15 | #include "config.h"
      |          ^~~~~~~~~~
compilation terminated.
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -std=c++14 -Iobj_dir -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/riscv -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/fesvr -I/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/ext/riscv-isa-sim/softfloat -I -lSDL2 -g -rdynamic -O3 -DTRACE  -std=gnu++14  -c -o VNaxRiscv__ConstPool_10.o VNaxRiscv__ConstPool_10.cpp
make[1]: *** [VNaxRiscv.mk:81: main.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: Leaving directory '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/src/test/cpp/naxriscv/obj_dir'
make: *** [makefile:94: compile] Error 2
make: Leaving directory '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv/src/test/cpp/naxriscv'

SpinalHDL / NaxRiscv

compiling code with updated codes #55