integrating both L2 cache miss counter and throttle

SoCScholar commented 8 months ago

I am wondering how can i integrate these both part of code which are in different location

NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala

https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala#L113

SpinalHDL/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala

https://github.com/SpinalHDL/SpinalHDL/blob/1f8a2fc205deed991a4d1e63795b6b43003a9b90/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala#L1063

I guess writing address 0xF30 wont be ok writing inside coherent/Cache.scala along with l2.cache

  scope.add(l2.cache.logic.cache.events.acquire.miss.pull() || l2.cache.logic.cache.events.getPut.miss.pull(), 0xF30)

This part of code scope.add( ) (memory mapped variable counter ) is very important for Bandwidth regulation.

  val readDown = new Area {
    val cmd = ctrl.process.toReadDown.pipelined(m2s = true, s2m = true)

    val BW_regulation_enable = Reg(Bool())  init(false) 
    csr.readWrite(BW_regulation_enable, 0x88X) // BW_regulation_enable configuring manually when we need or not need 

    scope.add(l2.cache.logic.cache.events.acquire.miss.pull() || l2.cache.logic.cache.events.getPut.miss.pull(), 0xF30) // I guess 0xF30 wont be enough writing here in this way. 

    when(some_condition) { // some regulation implementation 

                               val toDownA = cmd.haltWhen(throttle).swapPayload(io.down.a.payloadType()) // in case yes, we throttle as per we want to 

                               when (throttle) {  cycle_throttle := cycle_throttle+1  }  // to see cycle counter of how much CPU cycle it has been throttle 

                    }otherwise {  
                           val toDownA = cmd.swapPayload(io.down.a.payloadType()) // in case not, we let it be run in normal way
                                        }

    toDownA.opcode := Opcode.A.GET
    toDownA.param := 0
    toDownA.source := U"0" @@ cmd.gsId
    toDownA.address := cmd.address
    toDownA.size := cmd.size
    toDownA.mask.assignDontCare()
    toDownA.data.assignDontCare()
    toDownA.corrupt := False
    toDownA.debugId := DebugId.withPostfix(toDownA.source)

    }

Another Question

Will it be possible to throttle specific core from L2 cache in case there is too many miss happening from specific core of multicore?

I guess this is for whole L2 cache ( blocking accessing data for shared L2 cache )

``` Val toDownA = cmd.haltWhen(myCondition).swapPayload(io.down.a.payloadType())

Dolu1990 commented 8 months ago

Hi,

I do not understand what you mean by "how can i integrate"

You want to throttle a core accessing L2, based on cache miss he does on L2 ? If so, you only need to modify the Cache.scala. l2.cache.logic.cache is the instance of Cache.scala

Will it be possible to throttle specific core from L2 cache in case there is too many miss happening from specific core of multicore?

Yes

I guess this is for whole L2 cache ( blocking accessing data for shared L2 cache )

This is for the cache to send read requests to the DDR. (L2 cache refill)

Dolu1990 commented 8 months ago

One thing about the L2 cache design, is that it has a "replay queue" which could be used to easily throttle a specific core requests.

It is controlled by https://github.com/SpinalHDL/SpinalHDL/blob/dev/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala#L630C11-L630C18 , see the various condition at which this flag is set

Dolu1990 commented 8 months ago

So

redoUpA setWhen(!CTRL_CMD.probed && preCtrl.FROM_A && firstCycle && givenCpuThrottle)

You would then need to generate a proper givenCpuThrottle which depend on the CTRL_CMD.source

SoCScholar commented 8 months ago

as givenCpuThrottle comes from cache miss counter or from a memory-mapped counter

 ``` scope.add(l2.cache.logic.cache.events.acquire.miss.pull() || l2.cache.logic.cache.events.getPut.miss.pull(), 0xF30)```

How can I throttle specific core based on per Miss counter, which is equivalent to givenCpuThrottle?

How to supply givenCpuThrottle into /src/main/scala/spinal/lib/bus/tilelink/coherent/cache.scala from https://github.com/SpinalHDL/NaxSoftware/blob/8927ab57bb5b7f531d1c58fe96417bae2a264144/baremetal/socdemo/src/crt.S

  `redoUpA setWhen(!CTRL_CMD.probed && preCtrl.FROM_A && firstCycle && givenCpuThrottle)

Dolu1990 commented 8 months ago

How do you want to connect the counter to a bit ? I mean, how do you want to convert a miss counter into a throttle request ?

SoCScholar commented 8 months ago

Previously i did so

I incremented the counter by +1 as long as there is cache miss in every cycle.

i used later that counter to create some algorithm for throttling the CPU core

Dolu1990 commented 8 months ago

Here is an example of per CPU throttle : https://github.com/SpinalHDL/SpinalHDL/commit/f613a8878bcb32941fbfa24264fe273add91b76c

Dolu1990 commented 8 months ago

Then remains to add a control bus port to the l2 to make that throtteling configurable.

SoCScholar commented 8 months ago

Thank you so much.

Will it be possible to merge to the main branch of git because when I compile i just copied the necessary updated part of code and get some errors?

Then remains to add a control bus port to the l2 to make that throtteling configurable.
Yes. i guess it's very important

val missCost = 200

Instead of writing the misscost value manually 200, can we read the actual value?

I mean Can we read the missCost value based on L2 miss counter of specific core from L2 cache or the missCost value based on SCOPE_L2_AQUIRE_MISS + SCOPE_L2_GETPUT_MISS ?

    //show how many l2 cache miss happend
    la x1, SCOPE_L2_AQUIRE_MISS
    lw x10, 0(x1)
    la x1, SCOPE_L2_GETPUT_MISS
    lw x11, 0(x1)
    add x10, x10, x11

      add(l2c.events.acquire.hit, 0xF00) //acquire is used by data cache
          add(l2c.events.acquire.miss, 0xF04)
          add(l2c.events.getPut.hit, 0xF20) //getPut is used by instruction cache refill and DMA
          add(l2c.events.getPut.miss, 0xF24)
        }

Dolu1990 commented 8 months ago

Got it configurable:

Using https://github.com/SpinalHDL/NaxRiscv/tree/throttle_l2

And that assembly code :

  // Get the L2 cache ctrl address
  li x20, 0x10020000
  csrr x1, mhartid
  slli x1, x1, 4
  add x20, x20, x1

  // Set the miss cost
  li x1, 0x40
  sw x1, 0(x20)

  // Set the budget until throttle
  li x1, 0x200
  sw x1, 4(x20)
  la x1, data

  // run a endless sequancial load loop
  la x1, data
1:
  lw x2, 0(x1)
  addi x1, x1, 64
  j 1b

data:

Dolu1990 commented 8 months ago

(kinda based on https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.html#example-gpiofiber)

SoCScholar commented 8 months ago

thank you

can you please tell me how you compile (all steps please) the files which are in different git branch ?

How is it possible to see in gtkwaves also ?

Dolu1990 commented 8 months ago

you just need the NaxRiscv throttle_l2 branch cloned in a recursive manner, it include the SpinalHDL as a git module.

i did my test using opening the sbt shell in NaxRiscv and then runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 2 play.elf.zip

SoCScholar commented 8 months ago

Thank you so much :)

i am curious how can i get play.elf file when i run compile myself

Dolu1990 commented 8 months ago

Should be good with

cd ext/NaxSoftware/baremetal/play
replace src/crt.S content with that assembly code snippet 
make rv32ima

SoCScholar commented 8 months ago

sbt "runMain naxriscv.Gen64" && make -C src/test/cpp/naxriscv compile

can we do it by staying main branch in NaxRiscv and in dev branch in spainalHDL ?

Dolu1990 commented 8 months ago

no, SpinalHDL main is only for releases and is behind why switching branches to something else than throttle_l2 ?

SoCScholar commented 8 months ago

ok i stay in throttle_l2 in Main

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_throttle_branch/NaxRiscv$ git branch -a main

throttle_l2 remotes/origin/HEAD -> origin/main remotes/origin/asic remotes/origin/cleaning remotes/origin/coherency remotes/origin/dev remotes/origin/fast-reschedule remotes/origin/fix_fetch_cache_plugin_mem_rsp_ready remotes/origin/fpu remotes/origin/jtag remotes/origin/lsu2 remotes/origin/lsu_peripheral_store_cmd_ahead remotes/origin/main remotes/origin/reuse_licenses remotes/origin/riscv-debug remotes/origin/throttle_l2

but which branch to stay in SpinalHDL

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_throttle_branch/NaxRiscv/ext/SpinalHDL$ git branch -a

cache_throttle dev remotes/origin/AnalysisUtils_fix remotes/origin/HEAD -> origin/dev remotes/origin/PhaseCheckCrossClock-fix remotes/origin/async remotes/origin/bmbl2cache remotes/origin/bus-fabric remotes/origin/cache_throttle remotes/origin/commentRtlEntity remotes/origin/compiler_plugin_2.12 remotes/origin/contributor-guide remotes/origin/def_1.6.2 remotes/origin/dev remotes/origin/dma_fix remotes/origin/dolu remotes/origin/enum-merge remotes/origin/fifo-rework remotes/origin/fix-cc-meta remotes/origin/funding-yaml-1 remotes/origin/gh-pages remotes/origin/inout-fix remotes/origin/master remotes/origin/naxriscv remotes/origin/naxriscv_backup remotes/origin/pcie remotes/origin/riscv-debug remotes/origin/scala3 remotes/origin/scala3-dev remotes/origin/scala_2.12 remotes/origin/scala_2.12_dev remotes/origin/scala_2.13 remotes/origin/scala_2.13_dev remotes/origin/snoopy remotes/origin/soc_fmax remotes/origin/tilelink remotes/origin/tilelink-l2 remotes/origin/virtual-thread

SoCScholar commented 8 months ago

I get some errors by git checkout throttle_l2

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv$ git branch -a
* main
  remotes/origin/HEAD -> origin/main
  remotes/origin/asic
  remotes/origin/cleaning
  remotes/origin/coherency
  remotes/origin/dev
  remotes/origin/fast-reschedule
  remotes/origin/fix_fetch_cache_plugin_mem_rsp_ready
  remotes/origin/fpu
  remotes/origin/jtag
  remotes/origin/lsu2
  remotes/origin/lsu_peripheral_store_cmd_ahead
  remotes/origin/main
  remotes/origin/reuse_licenses
  remotes/origin/riscv-debug
  remotes/origin/throttle_l2
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv$ git checkout throttle_l2 
M   ext/NaxSoftware
M   ext/SpinalHDL
Branch 'throttle_l2' set up to track remote branch 'throttle_l2' from 'origin'.
Switched to a new branch 'throttle_l2'

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv$ sbt "runMain naxriscv.Gen64" && make -C src/test/cpp/naxriscv compile
[info] welcome to sbt 1.6.0 (Amazon.com Inc. Java 11.0.20.1)
[info] loading settings for project naxriscv-build from plugins.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv/ext/SpinalHDL/project
[info] loading settings for project all from build.sbt ...
[info] set current project to NaxRiscv (in build file:/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv/)
[info] compiling 1 Scala source to /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv/target/scala-2.11/classes ...
[error] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala:41:21: value throttleList is not a member of spinal.lib.bus.tilelink.coherent.CacheParam
[error]     cache.parameter.throttleList = naxes.map(_.plugins.collectFirst {case p : DataCachePlugin => p}.get)
[error]                     ^
[error] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala:64:25: value ctrl is not a member of spinal.lib.bus.tilelink.coherent.CacheFiber
[error]     if(withL2) l2.cache.ctrl at 0x20000 of bus
[error]                         ^
[error] two errors found
[error] (Compile / compileIncremental) Compilation failed
[error] Total time: 4 s, completed Nov 1, 2023, 3:12:52 PM

Dolu1990 commented 8 months ago

Same as specified by the git submodule. https://github.com/SpinalHDL/NaxRiscv/tree/throttle_l2/ext

i just did :

git clone --recursive --branch throttle_l2 https://github.com/SpinalHDL/NaxRiscv.git
cd NaxRiscv
sbt compile

All went fine can you try aswell from a fresh clone ?

SoCScholar commented 8 months ago

Thank you so much 🙏 🙏

How to use play.elf

where we can find files to load in GTK waves ? & which file is it (e.g. VCD) ? seems like .fst but couldnot find it

The error message suggests that the program is unable to locate the "iverilog-vpi" file, resulting in a "No such file or directory" error. This is likely causing the Java exception and the subsequent failure of the program to run.


[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] IVerilog compilation started
[error] Exception in thread "main" java.io.IOException: Cannot run program "iverilog-vpi": error=2, No such file or directory

i have following files


 hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/simWorkspace/SocDemo$ l
rtl/
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/simWorkspace/SocDemo$ cd rtl/
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/simWorkspace/SocDemo/rtl$ l
SocDemo.v                                                                               SocDemo.v_toplevel_naxes_1_thread_core_BtbPlugin_logic_mem.bin
SocDemo.v_toplevel_naxes_0_thread_core_BtbPlugin_logic_mem.bin                          SocDemo.v_toplevel_naxes_1_thread_core_DecoderPredictionPlugin_logic_ras_mem_stack.bin
SocDemo.v_toplevel_naxes_0_thread_core_DecoderPredictionPlugin_logic_ras_mem_stack.bin  SocDemo.v_toplevel_naxes_1_thread_core_GSharePlugin_logic_mem_counter.bin
SocDemo.v_toplevel_naxes_0_thread_core_GSharePlugin_logic_mem_counter.bin               SocDemo.v_toplevel_naxes_1_thread_core_Lsu2Plugin_logic_lq_hazardPrediction_mem.bin
SocDemo.v_toplevel_naxes_0_thread_core_Lsu2Plugin_logic_lq_hazardPrediction_mem.bin     SocDemo.v_toplevel_naxes_1_thread_core_Lsu2Plugin_logic_lq_hitPrediction_mem.bin
SocDemo.v_toplevel_naxes_0_thread_core_Lsu2Plugin_logic_lq_hitPrediction_mem.bin        SocDemo.v_toplevel_naxes_1_thread_core_RobPlugin_logic_completionMem_hits_0.bin
SocDemo.v_toplevel_naxes_0_thread_core_RobPlugin_logic_completionMem_hits_0.bin         SocDemo.v_toplevel_naxes_1_thread_core_RobPlugin_logic_completionMem_hits_1.bin
SocDemo.v_toplevel_naxes_0_thread_core_RobPlugin_logic_completionMem_hits_1.bin         SocDemo.v_toplevel_naxes_1_thread_core_RobPlugin_logic_completionMem_hits_2.bin
SocDemo.v_toplevel_naxes_0_thread_core_RobPlugin_logic_completionMem_hits_2.bin         SocDemo.v_toplevel_naxes_1_thread_core_RobPlugin_logic_completionMem_hits_3.bin
SocDemo.v_toplevel_naxes_0_thread_core_RobPlugin_logic_completionMem_hits_3.bin         SocDemo.v_toplevel_naxes_1_thread_core_RobPlugin_logic_completionMem_hits_4.bin
SocDemo.v_toplevel_naxes_0_thread_core_RobPlugin_logic_completionMem_hits_4.bin         SocDemo.v_toplevel_naxes_1_thread_core_RobPlugin_logic_completionMem_hits_5.bin
SocDemo.v_toplevel_naxes_0_thread_core_RobPlugin_logic_completionMem_hits_5.bin         SocDemo.v_toplevel_naxes_1_thread_core_RobPlugin_logic_completionMem_hits_6.bin
SocDemo.v_toplevel_naxes_0_thread_core_RobPlugin_logic_completionMem_hits_6.bin
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/simWorkspace/SocDemo/rtl$

I get following errors


hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv$ sbt
[info] welcome to sbt 1.6.0 (Amazon.com Inc. Java 11.0.20.1)
[info] loading settings for project naxriscv-build from plugins.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/ext/SpinalHDL/project
[info] loading settings for project all from build.sbt ...
[info] set current project to NaxRiscv (in build file:/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/)
[info] 
[info] Here are some highlights of this release:
[info]   - Improved JDK 17 support
[info]   - Improved Build Server Protocol (BSP) support
[info]   - Tab completion of global keys
[info] See https://eed3si9n.com/sbt-1.6.0 for full release notes.
[info] Hide the banner for this release by running `skipBanner`.
[info] sbt server started at local:///home/hsubedi/.sbt/1.0/server/d7b81577e183861766e5/sock
[info] started sbt server
sbt:NaxRiscv> compile
[success] Total time: 2 s, completed Nov 2, 2023, 12:17:20 PM
sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 2
[info] running (fork) naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 2
[info] [Runtime] SpinalHDL dev    git head : 3f9c287705429bbc0182cc415f187fc3e6b8eeeb
[info] [Runtime] JVM max memory : 7960.0MiB
[info] [Runtime] Current date : 2023.11.02 12:17:41
[info] [Progress] at 0.000 : Elaborate components
[info] [Progress] at 2.511 : Checks and transforms
[info] [Progress] at 4.134 : Generate Verilog
[info] [Warning] toplevel/naxes_0_thread_core/CommitPlugin_logic_free_lineEventStream_fifo/fifo/logic_ram : Mem[32*8 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/CommitPlugin_logic_free_lineEventStream_fifo/fifo/logic_ram : Mem[32*8 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfAllocationPlugin_logic_allocator/ways_0_mem : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RfAllocationPlugin_logic_allocator/ways_1_mem : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/ways_0_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/ways_0_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/ways_1_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/ways_1_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/ways_2_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/ways_2_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/ways_3_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/ways_3_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/status_mem : Mem[64*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/status_mem : Mem[64*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DataCachePlugin_logic_cache/plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/status_busy : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/status_busy : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/status_busy : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/status_busy : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/writes_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfTranslationPlugin_logic_impl/commits_ram : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfAllocationPlugin_logic_allocator/ways_0_mem : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RfAllocationPlugin_logic_allocator/ways_1_mem : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/ways_0_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/ways_0_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/ways_1_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/ways_1_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/ways_2_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/ways_2_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/ways_3_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/ways_3_mem : Mem[64*23 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/status_mem : Mem[64*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/status_mem : Mem[64*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DataCachePlugin_logic_cache/plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/integer_RegFilePlugin_logic_regfile_fpga/banks_0_ram : Mem[64*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/translation_physToRob : Mem[64*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/status_busy : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/status_busy : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/status_busy : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RfDependencyPlugin_logic_forRf_integer_impl/status_busy : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_logic_ways_0_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_logic_ways_1_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_logic_ways_2_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_logic_ways_3_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_logic_plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/BranchContextPlugin_logic_mem_earlyBranch : Mem[16*33 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/BranchContextPlugin_logic_mem_earlyBranch : Mem[16*33 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/BranchContextPlugin_logic_mem_finalBranch : Mem[16*65 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/DecoderPredictionPlugin_logic_ras_mem_stack : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_addressPre : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_addressPre : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_physRd : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_physRd : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_robIdMsb : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_pc : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_sqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_sqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_sqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_sqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_writeRd : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_writeRd : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_lr : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_unsigned : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_unsigned : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_doSpecial : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_needTranslation : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_hazardPrediction_valid : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_hazardPrediction_delta : Mem[16*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_lq_mem_hazardPrediction_score : Mem[16*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_robIdMsb : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_addressPre : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_addressPre : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_amo : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_amo : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_sc : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_sc : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_data : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_data : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_needTranslation : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_needTranslation : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_feededOnce : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_doSpecial : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_doNotBypass : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_logic_sq_mem_lqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_0 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_1 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_2 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_3 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_1_ways_0 : Mem[32*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_1_ways_1 : Mem[32*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_0 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_1 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_2 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_3 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_1_ways_0 : Mem[32*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_1_ways_1 : Mem[32*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/CsrRamPlugin_logic_mem : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/BranchContextPlugin_free_dispatchMem_mem : Mem[16*29 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_target : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Frontend_DISPATCH_MASK_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Frontend_DISPATCH_MASK_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PC_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PC_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PC_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PC_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PC_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PC_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PC_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PC_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PHYS_RD_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PHYS_RD_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_ARCH_RD_banks_0 : Mem[32*10 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PHYS_RD_FREE_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_BRANCH_SEL_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_BRANCH_HISTORY_banks_0 : Mem[32*24 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_BRANCH_HISTORY_banks_1 : Mem[32*24 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_DecoderPredictionPlugin_RAS_PUSH_PTR_banks_0 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_DecoderPredictionPlugin_RAS_PUSH_PTR_banks_1 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_LQ_ALLOC_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_SQ_ALLOC_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PHYS_RS_0_banks_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PHYS_RS_0_banks_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_READ_RS_0_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_READ_RS_0_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_READ_RS_0_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_READ_RS_0_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PHYS_RS_1_banks_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_PHYS_RS_1_banks_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_READ_RS_1_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_READ_RS_1_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_READ_RS_1_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_READ_RS_1_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_BRANCH_ID_banks_0 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_BRANCH_ID_banks_1 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_LSU_ID_banks_0 : Mem[32*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_LSU_ID_banks_1 : Mem[32*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_ROB_MSB_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_0_thread_core/RobPlugin_logic_storage_ROB_MSB_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_logic_ways_0_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_logic_ways_1_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_logic_ways_2_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_logic_ways_3_mem : Mem[64*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_logic_plru_ram : Mem[64*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/BranchContextPlugin_logic_mem_earlyBranch : Mem[16*33 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/BranchContextPlugin_logic_mem_earlyBranch : Mem[16*33 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/BranchContextPlugin_logic_mem_finalBranch : Mem[16*65 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/DecoderPredictionPlugin_logic_ras_mem_stack : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_addressPre : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_addressPre : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_physRd : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_physRd : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_robIdMsb : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_pc : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_sqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_sqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_sqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_sqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_writeRd : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_writeRd : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_lr : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_unsigned : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_unsigned : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_doSpecial : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_needTranslation : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_hazardPrediction_valid : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_hazardPrediction_delta : Mem[16*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_lq_mem_hazardPrediction_score : Mem[16*3 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_robId : Mem[16*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_robIdMsb : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_addressPre : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_addressPre : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_addressPost : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_size : Mem[16*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_io : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_amo : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_amo : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_sc : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_sc : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_data : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_data : Mem[16*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_needTranslation : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_needTranslation : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_feededOnce : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_doSpecial : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_doNotBypass : Mem[16*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_logic_sq_mem_lqAlloc : Mem[16*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_0 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_1 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_2 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_0_ways_3 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_1_ways_0 : Mem[32*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/FetchCachePlugin_setup_translationStorage_logic_sl_1_ways_1 : Mem[32*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_0 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_1 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_2 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_0_ways_3 : Mem[32*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_1_ways_0 : Mem[32*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/Lsu2Plugin_setup_translationStorage_logic_sl_1_ways_1 : Mem[32*22 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/CsrRamPlugin_logic_mem : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/BranchContextPlugin_free_dispatchMem_mem : Mem[16*29 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_target : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_1 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_2 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_3 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_4 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_5 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_completionMem_hits_6 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Frontend_DISPATCH_MASK_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Frontend_DISPATCH_MASK_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PC_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PC_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PC_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PC_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PC_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PC_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PC_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PC_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_WRITE_RD_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PHYS_RD_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PHYS_RD_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_ARCH_RD_banks_0 : Mem[32*10 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PHYS_RD_FREE_banks_0 : Mem[32*12 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_BRANCH_SEL_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Prediction_IS_BRANCH_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_BRANCH_TAKEN_banks_0 : Mem[64*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_BRANCH_HISTORY_banks_0 : Mem[32*24 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_BRANCH_HISTORY_banks_1 : Mem[32*24 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_DecoderPredictionPlugin_RAS_PUSH_PTR_banks_0 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_DecoderPredictionPlugin_RAS_PUSH_PTR_banks_1 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_LQ_ALLOC_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_SQ_ALLOC_banks_0 : Mem[32*2 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_0 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_Frontend_MICRO_OP_banks_1 : Mem[32*32 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PHYS_RS_0_banks_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PHYS_RS_0_banks_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_READ_RS_0_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_READ_RS_0_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_READ_RS_0_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_READ_RS_0_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PHYS_RS_1_banks_0 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_PHYS_RS_1_banks_1 : Mem[32*6 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_READ_RS_1_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_READ_RS_1_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_READ_RS_1_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_READ_RS_1_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_BRANCH_ID_banks_0 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_BRANCH_ID_banks_1 : Mem[32*4 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_LSU_ID_banks_0 : Mem[32*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_LSU_ID_banks_1 : Mem[32*5 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_ROB_MSB_banks_0 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/naxes_1_thread_core/RobPlugin_logic_storage_ROB_MSB_banks_1 : Mem[32*1 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/l2_cache_logic_cache/prober_ctx_ram : Mem[4*50 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/toplevel_naxes_0_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/toplevel_naxes_1_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] 1695 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 5.067
[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] IVerilog compilation started
[error] Exception in thread "main" java.io.IOException: Cannot run program "iverilog-vpi": error=2, No such file or directory
[error]     at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1128)
[error]     at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1071)
[error]     at scala.sys.process.ProcessBuilderImpl$Simple.run(ProcessBuilderImpl.scala:69)
[error]     at scala.sys.process.ProcessBuilderImpl$AbstractBuilder.$bang(ProcessBuilderImpl.scala:113)
[error]     at scala.sys.process.ProcessBuilderImpl$AbstractBuilder.slurp(ProcessBuilderImpl.scala:129)
[error]     at scala.sys.process.ProcessBuilderImpl$AbstractBuilder.$bang$bang(ProcessBuilderImpl.scala:102)
[error]     at spinal.sim.IVerilogBackend.<init>(IVerilogBackend.scala:59)
[error]     at spinal.core.sim.SpinalIVerilogBackend$Backend.<init>(SimBootstraps.scala:293)
[error]     at spinal.core.sim.SpinalIVerilogBackend$.apply(SimBootstraps.scala:307)
[error]     at spinal.core.sim.SpinalSimConfig.compile(SimBootstraps.scala:1060)
[error]     at spinal.core.sim.SpinalSimConfig.compileCloned(SimBootstraps.scala:934)
[error]     at spinal.core.sim.SpinalSimConfig.compile(SimBootstraps.scala:897)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.delayedEndpoint$naxriscv$platform$tilelinkdemo$SocSim$1(SocSim.scala:131)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$delayedInit$body.apply(SocSim.scala:52)
[error]     at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error]     at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error]     at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]     at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]     at scala.collection.immutable.List.foreach(List.scala:392)
[error]     at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error]     at scala.App$class.main(App.scala:76)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.main(SocSim.scala:52)
[error]     at naxriscv.platform.tilelinkdemo.SocSim.main(SocSim.scala)
[error] Caused by: java.io.IOException: error=2, No such file or directory
[error]     at java.base/java.lang.ProcessImpl.forkAndExec(Native Method)
[error]     at java.base/java.lang.ProcessImpl.<init>(ProcessImpl.java:340)
[error]     at java.base/java.lang.ProcessImpl.start(ProcessImpl.java:271)
[error]     at java.base/java.lang.ProcessBuilder.start(ProcessBuilder.java:1107)
[error]     ... 22 more
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 6 s, completed Nov 2, 2023, 12:17:46 PM
sbt:NaxRiscv>

Dolu1990 commented 8 months ago

Hi, ahhh the crash you had is because the sim was configured to use icarus verilog instead of verilator. I pushed a fix : https://github.com/SpinalHDL/NaxRiscv/commit/b664d4a985817808827eedf9791f005fed57b60d

How to use play.elf

That's an executable, you can give it to SoCSim via --load-elf play.elf arguement, it will load it

wave

Will be in NaxRiscv/simWorkspace/SocDemo/test.fst

SoCScholar commented 8 months ago

still i face errors

[info] [Warning] toplevel/toplevel_naxes_1_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] 1695 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 5.024
[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] Verilator compilation started
[info] ../verilator/VSocDemo__spinalWrapper.cpp: In function ‘void vl_finish(const char*, int, const char*)’:
[info] ../verilator/VSocDemo__spinalWrapper.cpp:582:16: error: ‘threadContextp’ is not a member of ‘Verilated’
[info]   582 |     Verilated::threadContextp()->gotFinish(true);
[info]       |                ^~~~~~~~~~~~~~
[info] make: *** [VSocDemo.mk:75: VSocDemo__spinalWrapper.o] Error 1
[info] make: *** Waiting for unfinished jobs....
[error] Exception in thread "main" java.lang.AssertionError: assertion failed: Verilator C++ model compilation failed
[error] make: Entering directory '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/simWorkspace/SocDemo/verilator'
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo__spinalWrapper.o ../verilator/VSocDemo__spinalWrapper.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o verilated.o /usr/share/verilator/include/verilated.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o verilated_fst_c.o /usr/share/verilator/include/verilated_fst_c.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo.o VSocDemo.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo_SocDemo.o VSocDemo_SocDemo.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo_SocDemo__1.o VSocDemo_SocDemo__1.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo_SocDemo__2.o VSocDemo_SocDemo__2.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo_Cache.o VSocDemo_Cache.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo_Cache__1.o VSocDemo_Cache__1.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo_Cache__2.o VSocDemo_Cache__2.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo_Cache__3.o VSocDemo_Cache__3.cpp
[error] g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -m64 -shared -Wno-attributes -I/usr/lib/jvm/java-11-amazon-corretto/include -I/usr/lib/jvm/java-11-amazon-corretto/include/linux -fvisibility=hidden -DVL_USER_FINISH=1 -O2 -DTRACE  -Os -c -o VSocDemo_NaxRiscv_1.o VSocDemo_NaxRiscv_1.cpp
[error] make: Leaving directory '/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/simWorkspace/SocDemo/verilator'
[error]     at scala.Predef$.assert(Predef.scala:170)
[error]     at spinal.sim.VerilatorBackend$$anonfun$compileVerilator$2.apply$mcV$sp(VerilatorBackend.scala:686)
[error]     at spinal.sim.VerilatorBackend.cacheSynchronized(VerilatorBackend.scala:75)
[error]     at spinal.sim.VerilatorBackend.compileVerilator(VerilatorBackend.scala:649)
[error]     at spinal.sim.VerilatorBackend.<init>(VerilatorBackend.scala:770)
[error]     at spinal.core.sim.SpinalVerilatorBackend$.apply(SimBootstraps.scala:144)
[error]     at spinal.core.sim.SpinalSimConfig.compile(SimBootstraps.scala:1003)
[error]     at spinal.core.sim.SpinalSimConfig.compileCloned(SimBootstraps.scala:934)
[error]     at spinal.core.sim.SpinalSimConfig.compile(SimBootstraps.scala:897)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.delayedEndpoint$naxriscv$platform$tilelinkdemo$SocSim$1(SocSim.scala:131)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$delayedInit$body.apply(SocSim.scala:52)
[error]     at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error]     at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error]     at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]     at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]     at scala.collection.immutable.List.foreach(List.scala:392)
[error]     at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error]     at scala.App$class.main(App.scala:76)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.main(SocSim.scala:52)
[error]     at naxriscv.platform.tilelinkdemo.SocSim.main(SocSim.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 14 s, completed Nov 2, 2023, 1:05:33 PM
sbt:NaxRiscv>

Dolu1990 commented 8 months ago

Which version of verilator do you have ? Me : verilator --version Verilator 4.218 2022-01-17 rev v4.218

SoCScholar commented 8 months ago

mine is

Verilator 4.038 2020-07-11 rev v4.036-114-g0cd4a57ad

kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/simWorkspace/SocDemo$

verilator --version Verilator 4.038 2020-07-11 rev v4.036-114-g0cd4a57ad

Dolu1990 commented 8 months ago

Ahhh that's tooo old

SoCScholar commented 8 months ago

i updated it and later i get another problem

now i have

Verilator 4.216 2021-12-05 rev v4.216

[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] Verilator compilation started
[info] [Progress] Verilator compilation done in 23185.034 ms
[info] [Progress] Start SocDemo test simulation with seed 2
[info] [Error] Simulation failed at time=0
[error] Exception in thread "main" java.lang.UnsatisfiedLinkError: Can't load library: /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/ext/rvls/build/apps/rvls.so
[error]     at java.base/java.lang.ClassLoader.loadLibrary(ClassLoader.java:2638)
[error]     at java.base/java.lang.Runtime.load0(Runtime.java:768)
[error]     at java.base/java.lang.System.load(System.java:1850)
[error]     at rvls.jni.Frontend.<clinit>(Frontend.java:35)
[error]     at naxriscv.platform.RvlsBackend.<init>(Tracer.scala:169)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$18.apply(SocSim.scala:154)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$18.apply(SocSim.scala:154)
[error]     at spinal.core.internals.BooleanPimped.generate(Misc.scala:285)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.testIt(SocSim.scala:154)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]     at spinal.core.sim.SimCompiled$$anonfun$doSimApi$1.apply$mcV$sp(SimBootstraps.scala:606)
[error]     at spinal.sim.SimThread$$anonfun$1.apply$mcV$sp(SimThread.scala:93)
[error]     at spinal.sim.JvmThread.run(SimManager.scala:51)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 30 s, completed Nov 2, 2023, 1:21:07 PM
sbt:NaxRiscv>

Dolu1990 commented 8 months ago

Ahh that's when ext/rvls isn't compiled.

So either you can build ext/rvls, either you use --no-rvls argument (never tested)

SoCScholar commented 8 months ago

I did so

sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 2 --no-rvls

did i did correctly ?

[info] [Warning] toplevel/toplevel_naxes_0_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/toplevel_naxes_1_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] 1695 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 5.352
[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] Verilator compilation started
[info] [info] Found cached verilator binaries
[info] [Progress] Verilator compilation done in 2509.503 ms
[info] [Progress] Start SocDemo test simulation with seed 2
[info] [Error] Simulation failed at time=0
[error] Exception in thread "main" java.nio.file.NoSuchFileException: play.elf
[error]     at java.base/sun.nio.fs.UnixException.translateToIOException(UnixException.java:92)
[error]     at java.base/sun.nio.fs.UnixException.rethrowAsIOException(UnixException.java:111)
[error]     at java.base/sun.nio.fs.UnixException.rethrowAsIOException(UnixException.java:116)
[error]     at java.base/sun.nio.fs.UnixFileSystemProvider.newByteChannel(UnixFileSystemProvider.java:219)
[error]     at java.base/java.nio.file.Files.newByteChannel(Files.java:371)
[error]     at java.base/java.nio.file.Files.newByteChannel(Files.java:422)
[error]     at java.base/java.nio.file.Files.readAllBytes(Files.java:3206)
[error]     at spinal.lib.misc.Elf.<init>(Elf.scala:10)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$testIt$5.apply(SocSim.scala:188)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$testIt$5.apply(SocSim.scala:187)
[error]     at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error]     at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.testIt(SocSim.scala:187)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]     at spinal.core.sim.SimCompiled$$anonfun$doSimApi$1.apply$mcV$sp(SimBootstraps.scala:606)
[error]     at spinal.sim.SimThread$$anonfun$1.apply$mcV$sp(SimThread.scala:93)
[error]     at spinal.sim.JvmThread.run(SimManager.scala:51)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 9 s, completed Nov 2, 2023, 1:27:34 PM
sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 2 --no-rvls

Dolu1990 commented 8 months ago

Exception in thread "main" java.nio.file.NoSuchFileException: play.elf

can't find play.elf So either you place play.elf in naxriscv folder, either you give relative path, either absolute path

SoCScholar commented 8 months ago

now it seems working

Should it be look like this ? I feel it might be stuck somewhere

info] [Warning] 1695 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 5.118
[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] Verilator compilation started
[info] [info] Found cached verilator binaries
[info] [Progress] Verilator compilation done in 2431.022 ms
[info] [Progress] Start SocDemo test simulation with seed 2
[info] Sim starting <3

how run in litex -->> FPGA ?

python3 -m litex_boards.targets.digilent_arty --variant a7-100 \
          --cpu-type naxriscv --xlen 64 --cpu-count 1 --l2-bytes 0 \
          --update-repo no --build

   python3 -m litex_boards.targets.digilent_arty --variant a7-100 \
          --cpu-type naxriscv --xlen 64 --cpu-count 1 --l2-bytes 0 \
          --update-repo no --load

Dolu1990 commented 8 months ago

[info] Sim starting <3

yes ^^

The SocSim isn't using the same SoC than litex. but it isn't much different

I guess with that special branch, l2.cache.ctrl at 0x20000 of bus is missing in NaxSoc

SoCScholar commented 8 months ago

Next day i again try to run again and i did following

i first run sbt server

sbt

then

compile

then

sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 2 --no-rvls

but i face some errors

Do you also get such errors ?

what can be cause of this errors

[error] Exception in thread "main" java.lang.NullPointerException

[info] [Warning] toplevel/toplevel_naxes_0_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/toplevel_naxes_1_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] 1695 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 5.286
[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv4_gtkwave/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] Verilator compilation started
[info] [info] Found cached verilator binaries
[info] [Progress] Verilator compilation done in 2377.761 ms
[info] [Progress] Start SocDemo test simulation with seed 2
[info] [Error] Simulation failed at time=0

[error] Exception in thread "main" java.lang.NullPointerException
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$testIt$1.apply$mcV$sp(SocSim.scala:172)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17$$anonfun$apply$4.apply(SocSim.scala:136)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17$$anonfun$apply$4.apply(SocSim.scala:136)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.testIt(SocSim.scala:165)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]     at spinal.core.sim.SimCompiled$$anonfun$doSimApi$1.apply$mcV$sp(SimBootstraps.scala:606)
[error]     at spinal.sim.SimThread$$anonfun$1.apply$mcV$sp(SimThread.scala:93)
[error]     at spinal.sim.JvmThread.run(SimManager.scala:51)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 9 s, completed Nov 5, 2023, 7:18:09 PM

SoCScholar commented 8 months ago

I guess with that special branch, l2.cache.ctrl at 0x20000 of bus is missing in NaxSoc

Will it be possible to update in following spinal.lib.bus.tilelink.coherent.CacheParam && spinal.lib.bus.tilelink.coherent.CacheFiber so It could run in Litex ?

Thank you so much

i get some errors like this


cd /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv && sbt "runMain naxriscv.platform.litex.NaxGen --netlist-name=NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009 --netlist-directory=/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog --reset-vector=0 --xlen=64 --cpu-count=1 --l2-bytes=4096 --l2-ways=8 --litedram-width=128 --memory-region=2147483648,2147483648,io,p --memory-region=0,131072,rxc,p --memory-region=268435456,8192,rwxc,p --memory-region=1073741824,268435456,rwxc,m --memory-region=4026531840,65536,rw,p --scala-file=/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/configs/gen.scala"
[info] welcome to sbt 1.6.0 (Amazon.com Inc. Java 11.0.20.1)
[info] loading settings for project naxriscv-build from plugins.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/ext/SpinalHDL/project
[info] loading settings for project all from build.sbt ...
[info] set current project to NaxRiscv (in build file:/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/)
[info] compiling 4 Scala sources to /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/target/scala-2.11/classes ...
[error] /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala:41:21: value throttleList is not a member of spinal.lib.bus.tilelink.coherent.CacheParam
[error]     cache.parameter.throttleList = naxes.map(_.plugins.collectFirst {case p : DataCachePlugin => p}.get)
[error]                     ^
[error] /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala:64:25: value ctrl is not a member of spinal.lib.bus.tilelink.coherent.CacheFiber
[error]     if(withL2) l2.cache.ctrl at 0x20000 of bus
[error]                         ^
[error] two errors found
[error] (Compile / compileIncremental) Compilation failed
[error] Total time: 5 s, completed Nov 3, 2023, 3:21:49 PM
Traceback (most recent call last):

The first error seems to suggest that throttleList is not recognized as a member of CacheParam, and the second error indicates that ctrl is not recognized as a member of CacheFiber.

Dolu1990 commented 8 months ago

With https://github.com/SpinalHDL/NaxRiscv/commit/f3a21af0ebde98c99cd319760deea953606700b7 ?

SoCScholar commented 8 months ago

Next day i again try to run again and i did following

i first run sbt server

sbt

then

compile

then

sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 2 --no-rvls

but i face some errors

Do you also get such errors ?

what can be cause of this errors

[error] Exception in thread "main" java.lang.NullPointerException

[info] [Warning] toplevel/toplevel_naxes_0_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] toplevel/toplevel_naxes_1_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] 1695 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 5.286
[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv4_gtkwave/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] Verilator compilation started
[info] [info] Found cached verilator binaries
[info] [Progress] Verilator compilation done in 2377.761 ms
[info] [Progress] Start SocDemo test simulation with seed 2
[info] [Error] Simulation failed at time=0

[error] Exception in thread "main" java.lang.NullPointerException
[error]   at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$testIt$1.apply$mcV$sp(SocSim.scala:172)
[error]   at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17$$anonfun$apply$4.apply(SocSim.scala:136)
[error]   at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17$$anonfun$apply$4.apply(SocSim.scala:136)
[error]   at naxriscv.platform.tilelinkdemo.SocSim$.testIt(SocSim.scala:165)
[error]   at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]   at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]   at spinal.core.sim.SimCompiled$$anonfun$doSimApi$1.apply$mcV$sp(SimBootstraps.scala:606)
[error]   at spinal.sim.SimThread$$anonfun$1.apply$mcV$sp(SimThread.scala:93)
[error]   at spinal.sim.JvmThread.run(SimManager.scala:51)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 9 s, completed Nov 5, 2023, 7:18:09 PM

what is the issue with [error] Exception in thread "main" java.lang.NullPointerException

Dolu1990 commented 8 months ago

What is SocSim.scala:172 on your codebase ?

SoCScholar commented 8 months ago

naxes.foreach { hart =>
        hart.add(tracerFile)
        val r = hart.backends.reverse
        hart.backends.clear()
        hart.backends ++= r
      }

Screenshot from 2023-11-06 15-26-19

Dolu1990 commented 8 months ago

Ahh with --no-rvls i can reproduce. Fixed with https://github.com/SpinalHDL/NaxRiscv/commit/0cf3661f7f4bd515c7aacf869dbaaa59830f23d5

SpinalHDL / NaxRiscv

integrating both L2 cache miss counter and throttle #58