64 bit risc v core from tilelink/socSim.scala.

[SoCScholar]

Dear charles,

I want to have 64 bit risc v core in tilelink/socSim.scala. i modify /platform/TilelinkNaxRiscvFiber.scala and it can compile the code but when i run 64 bit elf file in runMain naxriscv.platform.tilelinkdemo.SocSim it shows some strange errors

moreover, I am also wondering How can I add ScopeFiber() from tilelink/socSim.scala to Litex/NaxSoc.scala?

sbt

compile

sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf ext/NaxSoftware/baremetal/socdemo/build/rv64ima/socdemo.elf --trace --nax-count 2 --no-rvls

by making following changes

https://github.com/SpinalHDL/NaxRiscv/blob/throttle_l2/src/main/scala/naxriscv/platform/tilelinkdemo/SocDemo.scala#L19 https://github.com/SpinalHDL/NaxRiscv/blob/throttle_l2/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala#L84

line 19 of Socdemo.scala 

class SocDemo(cpuCount : Int, withL2 : Boolean = true, xlen : Int = 64, asic : Boolean = false) extends Component {

SocSim.Scala line 84

class SocDemoSim(cpuCount : Int) extends SocDemo(cpuCount, withL2 = withL2, xlen = 64, asic = asic){

gedit src/main/scala/naxriscv/platform/TilelinkNaxRiscvFiber.scala 

  def setCoherentConfig(hartId : Int, asic : Boolean = false) : this.type = {
    plugins load Config.plugins(
      withCoherency = true,
  +    xlen = 64,
      withRdTime = false,
      aluCount = 2,
      decodeCount = 2,
      ioRange = a => a(31 downto 28) === 0x1,
      hartId = hartId,
      asic = asic
    )

It throws strange errors. 

    [info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv5_gtkwave_5_Nov/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] Verilator compilation started
[info] [Progress] Verilator compilation done in 22154.623 ms
[info] [Progress] Start SocDemo test simulation with seed 2
[info] [Error] Simulation failed at time=0
[error] Exception in thread "main" java.lang.ArrayIndexOutOfBoundsException: Index 4096 out of bounds for length 4096
[error]     at spinal.lib.sim.SparseMemory.getElseAlocate(Misc.scala:134)
[error]     at spinal.lib.sim.SparseMemory.write(Misc.scala:163)
[error]     at spinal.lib.misc.Elf$$anonfun$load$1.apply(Elf.scala:39)
[error]     at spinal.lib.misc.Elf$$anonfun$load$1.apply(Elf.scala:35)
[error]     at spinal.lib.misc.Elf$$anonfun$foreachSection$1.apply$mcVI$sp(Elf.scala:16)
[error]     at scala.collection.immutable.Range.foreach$mVc$sp(Range.scala:160)
[error]     at spinal.lib.misc.Elf.foreachSection(Elf.scala:14)
[error]     at spinal.lib.misc.Elf.load(Elf.scala:35)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$testIt$5.apply(SocSim.scala:189)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$testIt$5.apply(SocSim.scala:187)
[error]     at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error]     at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.testIt(SocSim.scala:187)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$$anonfun$17.apply(SocSim.scala:136)
[error]     at spinal.core.sim.SimCompiled$$anonfun$doSimApi$1.apply$mcV$sp(SimBootstraps.scala:606)
[error]     at spinal.sim.SimThread$$anonfun$1.apply$mcV$sp(SimThread.scala:93)
[error]     at spinal.sim.JvmThread.run(SimManager.scala:51)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 30 s, completed Nov 9, 2023, 7:50:55 PM

Here we are running of socdemo by runMain naxriscv.platform.tilelinkdemo.SocSim in sbt server. If i wish to run this particular socdemo, which has probe of L2 cache miss in Litex/FPGA, it will be interesting to see result.

can you help me in tweeking of socdemo so it will be possible to run 64 bit risc v core and load 64 bit elf file ?

Thank you

[Dolu1990]

Should be ok now, got it to work with --load-elf ext/NaxSoftware/baremetal/dhrystone/build/rv64ima/dhrystone.elf --xlen 64

[SoCScholar]

With new gitpull

it does not work in sbt server

runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf ext/NaxSoftware/baremetal/socdemo/build/rv64ima/socdemo.elf --xlen 64 --trace --nax-count 2 --no-rvls 

it has following errors

 [info] [Warning] toplevel/toplevel_naxes_1_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog
[info] [Warning] 1617 signals were pruned. You can call printPruned on the backend report to get more informations.
[info] [Done] at 5.311
[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv5_gtkwave_5_Nov/naxRiscv5_24_11_2023/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] Verilator compilation started
[info] [Progress] Verilator compilation done in 22264.333 ms
[info] [Progress] Start SocDemo test simulation with seed 2
[info] Sim starting <3
[info] GET param=0 source=0 addr=0x0 bytes=4
[info] [Error] Simulation failed at time=7270
[error] Exception in thread "main" spinal.sim.SimFailure: 
[error]     at spinal.core.sim.package$.simFailure(package.scala:168)
[error]     at naxriscv.platform.PeripheralEmulator.onA(PeripheralEmulator.scala:71)
[error]     at spinal.lib.bus.tilelink.sim.Monitor$$anonfun$onA$1.apply(Monitor.scala:33)
[error]     at spinal.lib.bus.tilelink.sim.Monitor$$anonfun$onA$1.apply(Monitor.scala:33)
[error]     at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error]     at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error]     at spinal.lib.bus.tilelink.sim.Monitor.onA(Monitor.scala:33)
[error]     at spinal.lib.bus.tilelink.sim.Monitor$$anonfun$1.apply(Monitor.scala:44)
[error]     at spinal.lib.bus.tilelink.sim.Monitor$$anonfun$1.apply(Monitor.scala:44)
[error]     at spinal.lib.bus.tilelink.sim.TransactionAggregator.push(Transactions.scala:464)
[error]     at spinal.lib.bus.tilelink.sim.Monitor$$anonfun$7.apply(Monitor.scala:54)
[error]     at spinal.lib.bus.tilelink.sim.Monitor$$anonfun$7.apply(Monitor.scala:51)
[error]     at spinal.lib.sim.StreamMonitor$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(Stream.scala:33)
[error]     at spinal.lib.sim.StreamMonitor$$anonfun$1$$anonfun$apply$mcV$sp$1.apply(Stream.scala:33)
[error]     at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error]     at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error]     at spinal.lib.sim.StreamMonitor$$anonfun$1.apply$mcV$sp(Stream.scala:33)
[error]     at spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:969)
[error]     at spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:969)
[error]     at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error]     at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error]     at spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:969)
[error]     at spinal.core.sim.package$$anon$1.update(package.scala:194)
[error]     at spinal.sim.SimManager.runWhile(SimManager.scala:324)
[error]     at spinal.sim.SimManager.runAll(SimManager.scala:246)
[error]     at spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:606)
[error]     at spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:568)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.delayedEndpoint$naxriscv$platform$tilelinkdemo$SocSim$1(SocSim.scala:138)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$delayedInit$body.apply(SocSim.scala:52)
[error]     at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error]     at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error]     at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]     at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]     at scala.collection.immutable.List.foreach(List.scala:392)
[error]     at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error]     at scala.App$class.main(App.scala:76)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.main(SocSim.scala:52)
[error]     at naxriscv.platform.tilelinkdemo.SocSim.main(SocSim.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 29 s, completed Nov 24, 2023, 3:57:40 PM

sbt:NaxRiscv> 

[SoCScholar]

even this does not work

with 2 core

runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf ext/NaxSoftware/baremetal/dhrystone/build/rv64ima/dhrystone.elf --xlen 64 --trace --nax-count 2 --no-rvls

it throws following errors

[info] [Progress] Verilator compilation done in 2329.345 ms
[info] [Progress] Start SocDemo test simulation with seed 2
[info] Sim starting <3
[info] Dhrys
[info] toDnher yBsetnocnhem aBrekn,c Vhemrasriko,n  VersCi,o nV ersi
[info] on 2P.r2ogramP rocgormapmi lceodm pwiiltheodut  w'irethgoisstterer' 'a atttritbruitebu
[info] teUs
[info] ing time(), HZ=12000000
[info] Trying 500 runs through Dhrystone:
[info] [Error] Simulation failed at time=251970
[error] Exception in thread "main" spinal.sim.SimFailure: Nax didn't commited anything since too long
[error]     at spinal.core.sim.package$.simFailure(package.scala:168)
[error]     at naxriscv.platform.NaxriscvProbe.checkCommits(NaxriscvProbe.scala:212)
[error]     at naxriscv.platform.NaxriscvProbe$$anonfun$1.apply$mcV$sp(NaxriscvProbe.scala:334)
[error]     at spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:969)
[error]     at spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1$$anonfun$apply$mcV$sp$1.apply(package.scala:969)
[error]     at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error]     at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error]     at spinal.core.sim.package$SimClockDomainPimper$$anonfun$onSamplings$1.apply$mcV$sp(package.scala:969)
[error]     at spinal.core.sim.package$$anon$1.update(package.scala:194)
[error]     at spinal.sim.SimManager.runWhile(SimManager.scala:324)
[error]     at spinal.sim.SimManager.runAll(SimManager.scala:246)
[error]     at spinal.core.sim.SimCompiled.doSimApi(SimBootstraps.scala:606)
[error]     at spinal.core.sim.SimCompiled.doSimUntilVoid(SimBootstraps.scala:568)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.delayedEndpoint$naxriscv$platform$tilelinkdemo$SocSim$1(SocSim.scala:138)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$delayedInit$body.apply(SocSim.scala:52)
[error]     at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error]     at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error]     at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]     at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]     at scala.collection.immutable.List.foreach(List.scala:392)
[error]     at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error]     at scala.App$class.main(App.scala:76)
[error]     at naxriscv.platform.tilelinkdemo.SocSim$.main(SocSim.scala:52)
[error]     at naxriscv.platform.tilelinkdemo.SocSim.main(SocSim.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 13 s, completed Nov 24, 2023, 4:12:24 PM
sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --

[SoCScholar]

with 1 core i get following results

sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf ext/NaxSoftware/baremetal/dhrystone/build/rv64ima/dhrystone.elf --xlen 64 --trace --nax-count 1 --no-rvls

results

[info] [Done] at 3.941
[info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv5_gtkwave_5_Nov/naxRiscv5_24_11_2023/NaxRiscv/./simWorkspace/SocDemo
[info] [Progress] Verilator compilation started
[info] [info] Found cached verilator binaries
[info] [Progress] Verilator compilation done in 2332.374 ms
[info] [Progress] Start SocDemo test simulation with seed 2
[info] Sim starting <3
[info] Dhrystone Benchmark, Version C, Version 2.2
[info] Program compiled without 'register' attribute
[info] Using time(), HZ=12000000
[info] Trying 500 runs through Dhrystone:
[info] Measured time too small to obtain meaningful results
[info] Trying 5000 runs through Dhrystone:
[info] Final values of the variables used in the benchmark:
[info] Int_Glob:            5
[info]         should be:   5
[info] Bool_Glob:           1
[info]         should be:   1
[info] Ch_1_Glob:           A
[info]         should be:   A
[info] Ch_2_Glob:           B
[info]         should be:   B
[info] Arr_1_Glob[8]:       7
[info]         should be:   7
[info] Arr_2_Glob[8][7]:    5510
[info]         should be:   Number_Of_Runs + 10
[info] Ptr_Glob->
[info]   Ptr_Comp:          -2147463632
[info]         should be:   (implementation-dependent)
[info]   Discr:             0
[info]         should be:   0
[info]   Enum_Comp:         2
[info]         should be:   2
[info]   Int_Comp:          17
[info]         should be:   17
[info]   Str_Comp:          DHRYSTONE PROGRAM, SOME STRING
[info]         should be:   DHRYSTONE PROGRAM, SOME STRING
[info] Next_Ptr_Glob->
[info]   Ptr_Comp:          -2147463632
[info]         should be:   (implementation-dependent), same as above
[info]   Discr:             0
[info]         should be:   0
[info]   Enum_Comp:         1
[info]         should be:   1
[info]   Int_Comp:          18
[info]         should be:   18
[info]   Str_Comp:          DHRYSTONE PROGRAM, SOME STRING
[info]         should be:   DHRYSTONE PROGRAM, SOME STRING
[info] Int_1_Loc:           5
[info]         should be:   5
[info] Int_2_Loc:           13
[info]         should be:   13
[info] Int_3_Loc:           7
[info]         should be:   7
[info] Enum_Loc:            1
[info]         should be:   1
[info] Str_1_Loc:           DHRYSTONE PROGRAM, 1'ST STRING
[info]         should be:   DHRYSTONE PROGRAM, 1'ST STRING
[info] Str_2_Loc:           DHRYSTONE PROGRAM, 2'ND STRING
[info]         should be:   DHRYSTONE PROGRAM, 2'ND STRING
[info] Microseconds for one run through Dhrystone: 16
[info] Dhrystones per Second:                      62173
[info] User_Time : 965046
[info] Number_Of_Runs : 5000
[info] HZ : 12000000
[info] DMIPS per Mhz:                              2.94
[info] Hart 0
[info] - i$ refill = 67
[info] - d$ refill = 219
[info] [Done] Simulation done in 117282.105 ms
[success] Total time: 125 s (02:05), completed Nov 24, 2023, 4:14:37 PM

[Dolu1990]

even this does not work with 2 core

Dhrystone is only compiled to support 1 core. So it is normaly behaviour it crashes

[info] Sim starting <3 [info] GET param=0 source=0 addr=0x0 bytes=4 [info] [Error] Simulation failed at time=7270

The CPU do an access at address 0. What is your .asm from your software ?

[SoCScholar]

It works fine now in sbt as there was a mistake with the pass & fail symbol.

How can it be possible to run tilelink/socsim.scala in FPGA the way we run in SBT?

I guess below command line might not be helpful to run in FPGA.

runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf ext/NaxSoftware/baremetal/socdemo/build/rv64ima/socdemo.elf --xlen 64 --trace --nax-count 2 --no-rvls 

[Dolu1990]

SocSim isn't intented to be use in FPGA. Instead you could use the litex integration, which relay on NaxSoc.

[SoCScholar]

but how can i use those memory mapped value if i dont use SocSim

#define L2_CACHE_CTRL_BASE 0x10020000

#define SCOPE 0x14000000
#define SCOPE_L2_AQUIRE_MISS (SCOPE + 0xF04)
#define SCOPE_L2_GETPUT_MISS (SCOPE + 0xF24)
#define SCOPE_HART0 (SCOPE + 0*0x80) // 1st core index = 0 
#define SCOPE_HART_DCACHE_REFILL 0x10

#define SCOPE_HART_DCACHE_writeback 0x14

[Dolu1990]

you would need to port the modification done on the simulation soc toward NaxSoc

[SoCScholar]

Thank you so much.

I am trying to extend the memory mapped register for reading L2 cache miss, refill, WB count, throttle, but unfortunately I could not port the modification of scala code done in SocSim into NaxSoc to run into FPGA ( Litex)?

are there any other way to integrated socsim scala code in NaxSoc ? How to port the modification done on the simulation soc toward NaxSoc

[Dolu1990]

Step by step, little by little, starting with the L2 i would say.