LINUX on Litex_NaxRISCV ( Linux-capable, RISC-V-based SoC )

[SoCScholar]

Hi charles,

How will it be possible to run linux on Litex-Naxriscv like as https://github.com/litex-hub/linux-on-litex-vexriscv

I like to run (NaxRISCV 64 bit ) RISCV 64 Debian Linux on FPGA using Litex.

Thank you so much.

[Dolu1990]

Hi,

I don't remember, maybe forcing it to use naxriscv, did you tried the --help ?

[SoCScholar]

Dear Charles,

Thank you so much for your reply but I face many other difficulties too like issues during kernel boot && Kernel Initialization like initializing device drivers, and configuring system parameters. && Mounting the Root Filesystem & Launching User Space.. --help is unfortunately not enough.

I saw an example that has been done (https://github.com/roryt12/RISCV64-Debian-Linux-on-FPGA-with-Litex ) but when I am using it does not work for my 64-bit 2-cores NAXRISCV/Litex on LINUX. Can you please provide me with the necessary files like binary, Image, and .dtb?

Maybe I made a mistake in producing & compiling the latest OpenSBI binary

cp build/platform/litex/naxriscv_64/firmware/**fw_jump.bin**  ../**opensbi-naxriscv.bin**

What configuration do I have to organize here while creating the corresponding boot.json ?

{
        "Image"                 :       "0x41000000",
        "initrd.img-XXXX"           :       "0x42000000",
        "XXXX_XXXX.dtb"             :       "0x46000000",
        "opensbi-naxriscv.bin"      :       "0x40f00000"
}

Here I am trying to create a bitstream that has an ethernet port, and of rv64imafdc. Does NAX RISCV support such way to have 2 cores with ethernet and floating point double compressed ( fdc)

LOAD

python3 -m litex_boards.targets.digilent_arty --variant a7-100           --cpu-type naxriscv --with-ethernet --xlen 64 --cpu-count 2 --l2-bytes 131072           --update-repo no --eth-ip 192.168.1.51 --remote-ip  192.168.1.1 --load

build

python3 -m litex_boards.targets.digilent_arty --variant a7-100           --cpu-type naxriscv --with-ethernet --xlen 64 --cpu-count 2 --l2-bytes 131072           --update-repo no --eth-ip 192.168.1.51 --remote-ip  192.168.1.1 --build

[Dolu1990]

Here is some images i did had localy, not sure how good they are : https://drive.google.com/drive/folders/1dCTfbEv-6sD5hCpVzpG3LJQC0xOYc3RE?usp=drive_link

Note that is single code dts, and you need to check if the peripherals you have match the same address

[Dolu1990]

Not that if you already god a functional opensbi you don't need to take the one i sent

[SoCScholar]

How can we do for 2 cores? it mentioned something like this in below link

https://github.com/roryt12/RISCV64-Debian-Linux-on-FPGA-with-Litex

At this point you have to edit the files in the two directories to correspond to each core. For your convenience I have included mine. In order to compile the binary: NaxRiscv:

[Dolu1990]

rv32_2c_full_dma_sbi.dts.zip Here is an example of a 2 core dts, it is about the CPU definition, and the binding to the PLIC, that's all

[SoCScholar]

rv32_2c_full_dma_sbi.dts

Thank you for sending this nice dts file. I can see riscv,isa = "rv64imafdc"

is it for 64 bits? I am confused as if it is for 32 bits.

[SoCScholar]

Hi its says

Platform Name : LiteX / VexRiscv-SMP

[Dolu1990]

is it for 64 bits? I am confused as if it is for 32 bits.

Bad file name

Your issue seems that the main memory defined in the dts doesn't match your hardware

[SoCScholar]

Your issue seems that the main memory defined in the dts doesn't match your hardware

thank you for reply. Now this part is solved as to Linux boot process.

i tried to build and load in this way but It seems that Ethernet is missing in the dtb

python3 -m litex_boards.targets.digilent_arty --variant a7-100           --cpu-type naxriscv --with-ethernet --xlen 64 --cpu-count 2 --l2-bytes 131072           --update-repo no --eth-ip 192.168.1.51 --remote-ip  192.168.1.1 --with-rvc --with-fpu --load

https://github.com/SpinalHDL/NaxSoftware/tree/main/debian_litex#generate-a-dtb-from-a-dts

generally it should works as .dts already have liteeth part in mac for ethernet.

        mac@f0002000 {
            compatible = "litex,liteeth";
            reg = <0xf0002000 0x7c 0xf0002800 0x0a 0x80000000 0x2000>;
            reg-names = "mac\0mdio\0buffer";
            litex,rx-slots = <0x02>;
            litex,tx-slots = <0x02>;
            litex,slot-size = <0x800>;
            interrupts = <0x03>;
            status = "okay";
        };

after loading the image and finishing the Linux boot process i able to log in using the user ‘root’. I try to connect the board to an ethernet cable and configure an IP using the next command.

but it didnot work

root@buildroot:~#  ifconfig -a
lo        Link encap:Local Loopback  
          inet addr:127.0.0.1  Mask:255.0.0.0
          inet6 addr: ::1/128 Scope:Host
          UP LOOPBACK RUNNING  MTU:65536  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000 
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

sit0      Link encap:IPv6-in-IPv4  
          NOARP  MTU:1480  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000 
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

root@buildroot:~# 

[SoCScholar]

Dear Charles,

Would it be possible to change the setting for documentation of how to change for 2 cores Linux capable RISC-V computer system on an FPGA?

https://github.com/SpinalHDL/NaxRiscv/blob/main/src/test/cpp/naxriscv/README.md#run-linux

[Dolu1990]

Hi,

but it didnot work

Did you checked that the address mapping is right ? (f0002000) Did you checked that the interrupts mapping is right ? ( = <0x03>;) Did you checked the dmesg command for ethernet related error ?

Litex can change the address of things at elaboration time, depending what you configured.

https://github.com/SpinalHDL/NaxRiscv/blob/main/src/test/cpp/naxriscv/README.md#run-linux

This testbench is single core only.

[SoCScholar]

Did you checked that the address mapping is right ? (f0002000)

it dts file, i don't see where to put f0002000.

[Dolu1990]

i mean, check that the SoC generation you got from litex had the same f0002000 address for ethernet reg = <0xf0002000 0x7c 0xf0002800 0x0a 0x80000000 0x2000>;

Also, which linux kernel did you used ? (maybe it wasn't complied with the litex ethernet driver)

[SoCScholar]

reg = <0xf0002000 0x7c 0xf0002800 0x0a 0x80000000 0x2000>;

it did as I showed before:

https://github.com/SpinalHDL/NaxRiscv/issues/86#issuecomment-1989836877

        mac@f0002000 {
            compatible = "litex,liteeth";
            reg = <0xf0002000 0x7c 0xf0002800 0x0a 0x80000000 0x2000>;
            reg-names = "mac\0mdio\0buffer";
            litex,rx-slots = <0x02>;
            litex,tx-slots = <0x02>;
            litex,slot-size = <0x800>;
            interrupts = <0x03>;
            status = "okay";
        };

[SoCScholar]

Ethernet part is working for now

[Dolu1990]

Ethernet part is working for now

What was broken ?