Document Banana Memory Bus

[mithro]

From your README it says;

The BMB (Banana Memory Bus) which can cover both cached and cacheless SoC without compromises

Do you have any documentation on the BMB and why it can cover both cached and cacheless SoC without compromise.

[Dolu1990]

I just added that : https://github.com/SpinalHDL/SaxonSoc#bmb-spec-wip

The BMB bus itself is quite stable now, but the spec writting is WIP Basicaly it is the combination of the following factors :

• Not as complicated than AXI4
• Facilities to avoid having slave to implement burst support / unaligned access support
• State-less adapter made possible via the context feature
• Can do out of order stuff