Fix MII hardcoded parameter dataWidth

[roman3017]

NexysA7 uses RMII: http://ww1.microchip.com/downloads/en/DeviceDoc/8720a.pdf

Eth phy has dataWidth=2. The current patch is needed to change hardcoded dataWidth if we want to support RMII. Or I can try to use mii_to_rmii core on NexysA7 if we do not plan to support RMII.

But I still wonder what to do with RX_CLK and TX_CLK signals, which do not have pins. Are they necessary and is there a way not to bring them out? Should I drive REF_CLK with TX_CLK?

https://github.com/Digilent/digilent-xdc/blob/master/Nexys-A7-100T-Master.xdc

##SMSC Ethernet PHY
#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn

[roman3017]

Maybe dataWidth should not be configurable parameter for MII and we should create a proper RMII controller with non-configurable parameter dataWidth=2?

[roman3017]

It looks like eth phy on ArtyA7 supports both MII and RMII interfaces: https://www.ti.com/lit/ds/symlink/dp83848j.pdf

[roman3017]

Thinking more about it this PR to fit RMII to MII is wrong and I will close it.

[Dolu1990]

Hi, right, they are two similar but different things :)