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SpinalHDL / SaxonSoc

SoC based on VexRiscv and ICE40 UP5K
MIT License
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Fix sdram size #47

Closed dpavlin closed 4 years ago

dpavlin commented 4 years ago

Pass SDRAM_SIZE to saxon_netlist and example how to use it.

This is needed to fully support blue ULX3S board with 85F and 64Mb of SDRAM

Dolu1990 commented 4 years ago

Thanks, nice :)

dpavlin commented 4 years ago

Would it make sense to configure number of cpu cores based on size of FPGA or as build parameter?

Dolu1990 commented 4 years ago

I would say that the number of core should be a build parameter to give more freedoom. Currently, i just have to improve timings a bit to have it passing quadcore using yosys nextpnr.