Problem with SdramModel when changing sdram layout

[roman3017]

There seems to be a problem with SdramModel. In particular, one can run De1SocLinuxSystemSim without any issues with:

sbt "runMain saxon.board.terasic.De1SocLinuxSystemSim"

However, if one tries to change existing sdram layout from IS42x320D to either MT48LC16M16A2 or W9825G6JH6 one gets this exception:

[info] WAITING FOR TCP JTAG CONNECTION
[info] SDRAM : MODE REGISTER DEFINITION CAS=3 burstLength=0
[info] *** VexRiscv BIOS ***
[info] *** Supervisor ***
[info] Unknown exception 00000005
[info] machineModeSbi exception

To reproduce, please try this patch:

diff --git a/hardware/scala/saxon/board/terasic/De1SocLinux.scala b/hardware/scala/saxon/board/terasic/De1SocLinux.scala
index 42a7da0..81f5fc3 100644
--- a/hardware/scala/saxon/board/terasic/De1SocLinux.scala
+++ b/hardware/scala/saxon/board/terasic/De1SocLinux.scala
@@ -8,7 +8,7 @@ import spinal.lib.com.uart.UartCtrlMemoryMappedConfig
 import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder}
 import spinal.lib.generator._
 import spinal.lib.io.{Gpio, InOutWrapper}
-import spinal.lib.memory.sdram.IS42x320D
+import spinal.lib.memory.sdram.MT48LC16M16A2
 import spinal.lib.memory.sdram.sim.SdramModel

@@ -70,8 +70,8 @@ object De1SocLinuxSystem{
     cpu.config.load(VexRiscvConfigs.linux)
     cpu.enableJtag(clockCtrl)

-    sdramA.layout.load(IS42x320D.layout)
-    sdramA.timings.load(IS42x320D.timingGrade7)
+    sdramA.layout.load(MT48LC16M16A2.layout)
+    sdramA.timings.load(MT48LC16M16A2.timingGrade7)

     uartA.parameter load UartCtrlMemoryMappedConfig(
       baudrate = 115200,

Please let me know if there are any additional changes required when changing sdram layout.

[Dolu1990]

Did you changed the linux DTS to reflect the SDRAM capacity ?

println(s"W9825G6JH6 => ${W9825G6JH6.layout.capacity/1024/1024} MiB")
println(s"MT48LC16M16A2 => ${MT48LC16M16A2.layout.capacity/1024/1024} MiB")
println(s"IS42x320D => ${IS42x320D.layout.capacity/1024/1024} MiB")
=> 
W9825G6JH6 => 32 MiB
MT48LC16M16A2 => 32 MiB
IS42x320D => 64 MiB

It is likely the issue.

[roman3017]

@Dolu1990 the suggested change:

    memory@80400000 {
        device_type = "memory";
-       reg = <0x80400000 0x03C00000>;
+       reg = <0x80400000 0x01C00000>;
    };

indeed fixed the reported exception. The simulation passes the original problem and gets kernel panic later out of memory, which can be hopefully solved by further DTS changes and disabling some Linux features. We can close this. Thank you very much for your help.

[roman3017]

Just for the record, the following changes fixed for me the out of memory panic mentioned earlier:

diff --git a/board/spinal/saxon_default/linux.config b/board/spinal/saxon_default/linux.config
index ae8da96692..45d4c42f61 100644
--- a/board/spinal/saxon_default/linux.config
+++ b/board/spinal/saxon_default/linux.config
@@ -57,35 +57,6 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y

-# NET
-CONFIG_NET=y
-CONFIG_INET=y
-CONFIG_NETDEVICES=y
-
-CONFIG_PACKET=y
-CONFIG_PACKET_DIAG=y
-CONFIG_NET_PACKET_ENGINE=y
-
-CONFIG_NET_VENDOR_MICROCHIP=y
-CONFIG_ENC28J60=y
-
-CONFIG_NET_VENDOR_WIZNET=y
-CONFIG_WIZNET_BUS_ANY=y
-CONFIG_WIZNET_W5100=y
-CONFIG_WIZNET_W5100_SPI=y
-
-# WIFI
-CONFIG_STAGING=y
-CONFIG_CFG80211=y
-CONFIG_NL80211_TESTMODE=y
-CONFIG_CFG80211_DEVELOPER_WARNINGS=y
-CONFIG_CFG80211_WEXT=y
-CONFIG_MAC80211=y
-##CONFIG_WILC1000=y
-##CONFIG_WILC1000_SPI=y
-CONFIG_WLAN_VENDOR_MCHP=y
-CONFIG_WILC=y
-CONFIG_WILC_SPI=y
 CONFIG_PM=y
 CONFIG_HOSTAP=y
 CONFIG_HOSTAP_FIRMWARE=y
diff --git a/board/spinal/saxon_default/spinal_saxon_default_de1_soc.dts b/board/spinal/saxon_default/spinal_saxon_default_de1_soc.dts
index 8e0e2e665c..8e9d802f74 100644
--- a/board/spinal/saxon_default/spinal_saxon_default_de1_soc.dts
+++ b/board/spinal/saxon_default/spinal_saxon_default_de1_soc.dts
@@ -14,8 +14,8 @@

     chosen {
         bootargs = "rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32"; // loglevel=7
-        linux,initrd-start = <0x80C00000>;
-        linux,initrd-end =   <0x82000000>; 
+        linux,initrd-start = <0x80800000>;
+        linux,initrd-end =   <0x81000000>; 
     };

@@ -40,7 +40,7 @@

     memory@80400000 {
         device_type = "memory";
-        reg = <0x80400000 0x03C00000>;
+        reg = <0x80400000 0x01C00000>;
     };

     apbA@10000000 {

diff --git a/hardware/scala/saxon/board/terasic/De1SocLinux.scala b/hardware/scala/saxon/board/terasic/De1SocLinux.scala
index 42a7da0..fcf5cab 100644
--- a/hardware/scala/saxon/board/terasic/De1SocLinux.scala
+++ b/hardware/scala/saxon/board/terasic/De1SocLinux.scala
@@ -8,7 +8,7 @@ import spinal.lib.com.uart.UartCtrlMemoryMappedConfig
 import spinal.lib.com.uart.sim.{UartDecoder, UartEncoder}
 import spinal.lib.generator._
 import spinal.lib.io.{Gpio, InOutWrapper}
-import spinal.lib.memory.sdram.IS42x320D
+import spinal.lib.memory.sdram._
 import spinal.lib.memory.sdram.sim.SdramModel

@@ -70,8 +70,8 @@ object De1SocLinuxSystem{
     cpu.config.load(VexRiscvConfigs.linux)
     cpu.enableJtag(clockCtrl)

-    sdramA.layout.load(IS42x320D.layout)
-    sdramA.timings.load(IS42x320D.timingGrade7)
+    sdramA.layout.load(W9825G6JH6.layout)
+    sdramA.timings.load(W9825G6JH6.timingGrade7)

     uartA.parameter load UartCtrlMemoryMappedConfig(
       baudrate = 115200,
@@ -215,8 +215,8 @@ object De1SocLinuxSystemSim {
       val linuxPath = "../buildroot/output/images/"
       sdram.loadBin(0x00000000, "software/standalone/machineModeSbi/build/machineModeSbi.bin")
       sdram.loadBin(0x00400000, linuxPath + "Image")
-      sdram.loadBin(0x00BF0000, linuxPath + "dtb")
-      sdram.loadBin(0x00C00000, linuxPath + "rootfs.cpio")
+      sdram.loadBin(0x007F0000, linuxPath + "dtb")
+      sdram.loadBin(0x00800000, linuxPath + "rootfs.cpio")

 //      sdram.loadBin(0, "software/standalone/dhrystone/build/dhrystone.bin")
diff --git a/software/standalone/machineModeSbi/src/config.h b/software/standalone/machineModeSbi/src/config.h
index 32c4175..87f5c17 100644
--- a/software/standalone/machineModeSbi/src/config.h
+++ b/software/standalone/machineModeSbi/src/config.h
@@ -5,6 +5,6 @@
 //#define SIM
 #define HARD
 #define OS_CALL 0x80400000
-#define DTB     0x80BF0000
+#define DTB     0x807F0000

 #endif

[Dolu1990]

Thanks :)

[Dolu1990]

@roman3017 Are you interrested into Saxon ? There is so many things to do XD So if you want to contribut, you are welcome ^^ Also, i'm currently working on a new SDRAM controller (SDR, DDRx)

[roman3017]

@Dolu1990: I am interested although sometime I am too busy with my daily tasks. I am working on making Saxon to work on Scarab (MiniSpartan6+) HW, which is why I needed this change. This is the only FPGA board with SDRAM I have. Once you have DDR controller, things will be easier for me, since I can use Zybo board with DDR2 or Nexys4DDR with DDR3. I am also wondering about: https://www.electronicdesign.com/embedded-revolution/xip-linux-new-spin-embedded-architecture https://elinux.org/RZ-A/Boards/GR-PEACH-bsp In particular it would be great if we can run Linux on FPGA board without SDRAM. But it may require too much BRAM. I will contribute what I have and have started to follow your Gitter conversation.

[Dolu1990]

Ok :D Let's me know how it goes.

I just moved the SDRAM controller from the spinal.lib.memory.sdram package to the spinal.lib.memory.sdram.sdr package.