roman3017
commented
3 years ago @mithro: I have tried symbiflow but getting this error when trying to synthesize NexysA7SmpLinux with symbiflow_synth:
make -f symbiflow.mk
cd build_symbiflow && symbiflow_synth -t NexysA7SmpLinux -v /.../SaxonSoc/hardware/synthesis/digilent/NexysA7SmpLinux/../../../netlist/NexysA7SmpLinux.v -d artix7 -p xc7a100tcsg324-1 2>&1 > /dev/null
ERROR: Module `\Ram_1w_1rs' referenced in module `\DataCache' in cell `\ways_1_data' is not part of the design.
make: *** [symbiflow.mk:28: build_symbiflow/NexysA7SmpLinux.eblif] Error 1Here is my makefile symbiflow.mk:
# cd hardware/synthesis/digilent/NexysA7SmpLinux/
# make generate
# export INSTALL_DIR=/opt/symbiflow
# export PATH="$INSTALL_DIR/xc7/install/bin:$PATH"
# source "$INSTALL_DIR/xc7/conda/etc/profile.d/conda.sh"
# conda activate xc7
# make -f symbiflow.mk
# conda deactivate
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
TOP:=NexysA7SmpLinux
VERILOG:=${current_dir}/../../../netlist/$(TOP).v
BITSTREAM_DEVICE := artix7
SDC:=${current_dir}/NexysA7.xdc
BUILDDIR:=build_symbiflow
PARTNAME:= xc7a100tcsg324-1
PCF:=${current_dir}/arty.pcf
DEVICE:= xc7a100t_test
all: ${BUILDDIR}/${TOP}.bit
${BUILDDIR}:
mkdir ${BUILDDIR}
${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
cd ${BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
cd ${BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.place: ${BUILDDIR}/${TOP}.net
cd ${BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.route: ${BUILDDIR}/${TOP}.place
cd ${BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.fasm: ${BUILDDIR}/${TOP}.route
cd ${BUILDDIR} && symbiflow_write_fasm -e ${TOP}.eblif -d ${DEVICE}
${BUILDDIR}/${TOP}.bit: ${BUILDDIR}/${TOP}.fasm
cd ${BUILDDIR} && symbiflow_write_bitstream -d ${BITSTREAM_DEVICE} -f ${TOP}.fasm -p ${PARTNAME} -b ${TOP}.bit
clean:
rm -rf ${BUILDDIR}
Dolu1990
The SymbiFlow project is slowly getting pretty decent support for the Xilinx Artix 7 part and more specifically the Digilent Arty A7 board. It would be awesome to have a SaxonSoC design in the SymbiFlow Examples repository so we can make sure the design works with the fully open source tooling (we already have a Linux + LiteX with VexRISCV design example working). I logged https://github.com/SymbiFlow/symbiflow-examples/issues/74) on the SymbiFlow Examples.
It might also good to get SaxonSoC into the SymbiFlow fpga-tool-perf as a test design -- that way we can track how the performance is improved over time (and how the open tools compares to options like Vivado). (Logged https://github.com/SymbiFlow/fpga-tool-perf/issues/278 for that.)