search

SpinalHDL / SaxonSoc

SoC based on VexRiscv and ICE40 UP5K
MIT License
150 stars 40 forks source link

I want to change cpu config in Ulx3SMinimal.scala,but got error. #66

Closed jmio closed 3 years ago

jmio commented 3 years ago

Hi.

I have started to use SaxonSoC. To change the CPU settings, I have changed the configuration part of Ulx3SMinimal.scala.

Like...

 //cpu.config.load(VexRiscvConfigs.minimal)
 cpu.config.load(VexRiscvConfigs.muraxLike)

I got the following error.

Why is this? What should I do?

[error] Exception in thread "main" spinal.core.SpinalExit:
[error]  Error detected in phase PhaseCheck_noLatchNoOverride
[error] ********************************************************************************
[error] ********************************************************************************
[error] NO DRIVER ON (toplevel/system_cpu_logic_cpu/timerInterrupt : in Bool), defined at
[error]     vexriscv.plugin.CsrPlugin.setup(CsrPlugin.scala:590)
[error]     vexriscv.plugin.CsrPlugin.setup(CsrPlugin.scala:434)
[error]     vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
[error]     vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
[error]     vexriscv.Pipeline$class.build(Pipeline.scala:47)
[error]     vexriscv.VexRiscv.build(VexRiscv.scala:122)
[error]     vexriscv.Pipeline$$anonfun$1.apply$mcV$sp(Pipeline.scala:161)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7$$anon$2.<init>(VexRiscvBmbGenerator.scala:95)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7.apply(VexRiscvBmbGenerator.scala:90)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7.apply(VexRiscvBmbGenerator.scala:90)
[error]     spinal.sim.JvmThread.run(SimManager.scala:51)
[error] ********************************************************************************
[error] ********************************************************************************
[error] NO DRIVER ON (toplevel/system_cpu_logic_cpu/externalInterrupt : in Bool), defined at
[error]     vexriscv.plugin.CsrPlugin.setup(CsrPlugin.scala:591)
[error]     vexriscv.plugin.CsrPlugin.setup(CsrPlugin.scala:434)
[error]     vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
[error]     vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
[error]     vexriscv.Pipeline$class.build(Pipeline.scala:47)
[error]     vexriscv.VexRiscv.build(VexRiscv.scala:122)
[error]     vexriscv.Pipeline$$anonfun$1.apply$mcV$sp(Pipeline.scala:161)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7$$anon$2.<init>(VexRiscvBmbGenerator.scala:95)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7.apply(VexRiscvBmbGenerator.scala:90)
[error]     vexriscv.VexRiscvBmbGenerator$$anonfun$7.apply(VexRiscvBmbGenerator.scala:90)
[error]     spinal.sim.JvmThread.run(SimManager.scala:51)
[error] ********************************************************************************
[error] ********************************************************************************
Dolu1990 commented 3 years ago

you need to manage the interrupts. Do you want them ?

It isn't exactly the same situation, but in the linux soc it is manged as : https://github.com/SpinalHDL/SaxonSoc/blob/440ff0eca051e117a47d6e83fb87c6b1e8ec0f1a/hardware/scala/saxon/VexRiscvClusterGenerator.scala#L34

jmio commented 3 years ago

Thank you .

I don't need external interrupts at the moment, but I do need timer interrupts.

I tried to mimic it as follows, 

.....
  implicit val cpu = VexRiscvBmbGenerator()

  interconnect.setDefaultArbitration(BmbInterconnectGenerator.STATIC_PRIORITY)
  interconnect.setPriority(cpu.iBus, 1)
  interconnect.setPriority(cpu.dBus, 2)

  val clint = BmbClintGenerator(0xB00000) //Used as a time reference only
  clint.cpuCount.load(0)

  cpu.setTimerInterrupt(clint.timerInterrupt(0))  // <====== Add This line

  //Add components
  val ramA = BmbOnChipRamGenerator(0x80000000l) // 32K Code
....

but got another error (^^;


[info] ! SpinalHDL async engine is stuck !
[info] Waiting on system_cpu_timerInterrupt defined at ???:
[info] 1) ??? loader
[info] **********************************************************************************************
[info] [Warning] Elaboration failed (0 error).
[info]           Spinal will restart with scala trace to help you to find the problem.
[info] **********************************************************************************************
[info] [Progress] at 1.154 : Elaborate components
[info] ! SpinalHDL async engine is stuck !
[info] Waiting on system_cpu_timerInterrupt defined at vexriscv.VexRiscvBmbGenerator.<init>(VexRiscvBmbGenerator.scala:34):
[info] 1) ??? loader
[error] Exception in thread "main" java.lang.Exception: SpinalHDL async engine is stuck
[error]         at spinal.core.fiber.EngineContext.start(AsyncCtrl.scala:124)
[error]         at spinal.core.fiber.Engine$.create(AsyncCtrl.scala:150)
[error]         at spinal.core.internals.PhaseCreateComponent.impl(Phase.scala:2235)
[error]         at spinal.core.internals.PhaseContext.doPhase(Phase.scala:181)
[error]         at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$120.apply(Phase.scala:2538)
[error]         at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$120.apply(Phase.scala:2536)
[error]         at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error]         at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error]         at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2536)
[error]         at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2473)
[error]         at spinal.core.ScopeProperty$.sandbox(ScopeProperty.scala:32)
[error]         at spinal.core.internals.SpinalVerilogBoot$.singleShot(Phase.scala:2473)
[error]         at spinal.core.internals.SpinalVerilogBoot$.apply(Phase.scala:2468)
[error]         at spinal.core.Spinal$.apply(Spinal.scala:371)
[error]         at spinal.core.SpinalConfig.generateVerilog(Spinal.scala:164)
[error]         at saxon.board.muselab.ICESugarPro.ICESugarProMinimal$.delayedEndpoint$saxon$board$muselab$ICESugarPro$ICESugarProMinimal$1(ICESugarProMinimal.scala:213)
[error]         at saxon.board.muselab.ICESugarPro.ICESugarProMinimal$delayedInit$body.apply(ICESugarProMinimal.scala:204)
[error]         at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error]         at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error]         at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]         at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]         at scala.collection.immutable.List.foreach(List.scala:392)
[error]         at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error]         at scala.App$class.main(App.scala:76)
[error]         at saxon.board.muselab.ICESugarPro.ICESugarProMinimal$.main(ICESugarProMinimal.scala:204)
[error]         at saxon.board.muselab.ICESugarPro.ICESugarProMinimal.main(ICESugarProMinimal.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 10 s, completed 2021/10/01 6:52:55
jmio commented 3 years ago

Sorry, the error above was my fault.

cpu.config.load(VexRiscvConfigs.minimal)
jmio commented 3 years ago

However, I still got the following error (^^;

[error] Exception in thread "main" spinal.core.SpinalExit:
[error]  Error detected in phase PhaseNormalizeNodeInputs
[error] ********************************************************************************
[error] ********************************************************************************
[error] Static bool extraction (bit 0) is outside the range (-1 downto 0) of (toplevel/system_clint_logic/io_timerInterrupt : out Bits[0 bits]) at
[error]     spinal.lib.bus.bmb.BmbClintGenerator$$anonfun$timerInterrupt$1.apply(BmbGenerators.scala:95)
[error]     spinal.lib.bus.bmb.BmbClintGenerator$$anonfun$timerInterrupt$1.apply(BmbGenerators.scala:95)
[error]     spinal.sim.JvmThread.run(SimManager.scala:51)
[error] ********************************************************************************
[error] ********************************************************************************
Dolu1990 commented 3 years ago

Ho did you instanciated the clint ?

Dolu1990 commented 3 years ago

If you don't want the clint as a timer, then you should not use its io_timerInterrupt You can just tie the CPU timer input to False ^^

jmio commented 3 years ago

I read the definitions of BmbClintGenerator, BmbClint and Clint. If cpuCount = 0, then no signal line is generated, right?

  val clint = BmbClintGenerator(0xB00000) 
  clint.cpuCount.load(1) // must not 0!
jmio commented 3 years ago

It also worked on the actual machine. Thank you.

The behavior of interrupts seems to be different from Briey, so I'll ask again if I don't understand.

Dolu1990 commented 3 years ago

If cpuCount = 0, then no signal line is generated, right?

Right, 1 timer per cpu ^^

The behavior of interrupts seems to be different from Briey, so I'll ask again if I don't understand.

Yes, the behaviour is very different. SaxonSoc follow the "standard" risc-v way (combo plic / clint)

jmio commented 3 years ago

Hi,

I'm learning how to use "SaxonSoc" by modifying "Minimal" Sample little by little.

Now , I'm trying to add VGA and DMA for it by referring to the ULX3S SMP sample, but I'm getting the following error.... ^^;

...

  implicit val bsbInterconnect = BsbInterconnectGenerator()
  val dma = new DmaSgGenerator(0x80000){
    val vga = new Area{
      val channel = createChannel()
      channel.fixedBurst(64)
      channel.withCircularMode()
      channel.fifoMapping load Some(0, 256)
      channel.connectInterrupt(plic, 12)

      val stream = createOutput(byteCount = 4)
      channel.outputsPorts += stream
    }
  }

  val dBus32 = BmbBridgeGenerator()
  dBus32.dataWidth(32) //Avoid 64 bits FPU requirements getting further

  //interconnect.addConnection(dma.write,   dBus32.bmb)
  interconnect.addConnection(dma.read,    dBus32.bmb)
  interconnect.addConnection(dma.readSg,  dBus32.bmb)
  interconnect.addConnection(dma.writeSg, dBus32.bmb)

  val vga = BmbVgaCtrlGenerator(0x90000)
  bsbInterconnect.connect(dma.vga.stream.output, vga.input)

  //Interconnect specification
  interconnect.setDefaultArbitration(BmbInterconnectGenerator.STATIC_PRIORITY)
  interconnect.setPriority(cpu.iBus, 1)
  interconnect.setPriority(cpu.dBus, 2)
  interconnect.addConnection(
    cpu.iBus   -> List(dBus32.bmb),//sdramA0.bmb,ramA.ctrl, bmbPeripheral.bmb),
    //fabric.dBus.bmb   -> List(sdramA0.bmb,ramA.ctrl, bmbPeripheral.bmb)
    cpu.dBus   -> List(dBus32.bmb),
    dBus32.bmb -> List(sdramA0.bmb,ramA.ctrl, bmbPeripheral.bmb)
  )
...
[info] running (fork) saxon.board.muselab.ICESugarPro.ICESugarProMinimal
[info] [Runtime] SpinalHDL v1.6.1    git head : 8434600e3b32dc561f4e361e99a6085b79085453
[info] [Runtime] JVM max memory : 2738.0MiB
[info] [Runtime] Current date : 2021.10.12 06:49:14
[info] [Progress] at 0.000 : Elaborate components
[info] ! SpinalHDL async engine is stuck !
[info] Waiting on system_dma_readSg_masterModel_accessRequirements defined at ???:
[info] 1) system_dma_readSg_masterModel_decoderGen, ???, ??? loader
[info] 2) ??? loader
[info] 3) system_dBus32_bmb_slaveModel_accessSource loader
[info] Waiting on system_dma_writeSg_masterModel_accessRequirements defined at ???:
[info] 1) system_dma_writeSg_masterModel_decoderGen, ???, ??? loader
[info] 2) ??? loader
[info] **********************************************************************************************
[info] [Warning] Elaboration failed (0 error).
[info]           Spinal will restart with scala trace to help you to find the problem.
[info] **********************************************************************************************
[info] [Progress] at 1.465 : Elaborate components
[info] ! SpinalHDL async engine is stuck !
[info] Waiting on system_dma_readSg_masterModel_accessRequirements defined at spinal.lib.bus.bmb.BmbInterconnectGenerator$MasterModel.<init>(BmbInterconnectGenerator.scala:34):
[info] 1) system_dma_readSg_masterModel_decoderGen, ???, ??? loader
[info] 2) ??? loader
[info] 3) system_dBus32_bmb_slaveModel_accessSource loader
[info] Waiting on system_dma_writeSg_masterModel_accessRequirements defined at spinal.lib.bus.bmb.BmbInterconnectGenerator$MasterModel.<init>(BmbInterconnectGenerator.scala:34):
[error] Exception in thread "main" java.lang.Exception: SpinalHDL async engine is stuck
[info] 1) system_dma_writeSg_masterModel_decoderGen, ???, ??? loader
[error]         at spinal.core.fiber.EngineContext.start(AsyncCtrl.scala:124)
[error]         at spinal.core.fiber.Engine$.create(AsyncCtrl.scala:150)
[error]         at spinal.core.internals.PhaseCreateComponent.impl(Phase.scala:2235)
[error]         at spinal.core.internals.PhaseContext.doPhase(Phase.scala:181)
[info] 2) ??? loader
[error]         at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$120.apply(Phase.scala:2538)
[error]         at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$120.apply(Phase.scala:2536)
[error]         at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error]         at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error]         at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2536)
[error]         at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2473)
[error]         at spinal.core.ScopeProperty$.sandbox(ScopeProperty.scala:32)
[error]         at spinal.core.internals.SpinalVerilogBoot$.singleShot(Phase.scala:2473)
[error]         at spinal.core.internals.SpinalVerilogBoot$.apply(Phase.scala:2468)
[error]         at spinal.core.Spinal$.apply(Spinal.scala:371)
[error]         at spinal.core.SpinalConfig.generateVerilog(Spinal.scala:164)
[error]         at saxon.board.muselab.ICESugarPro.ICESugarProMinimal$.delayedEndpoint$saxon$board$muselab$ICESugarPro$ICESugarProMinimal$1(ICESugarProMinimal.scala:360)
[error]         at saxon.board.muselab.ICESugarPro.ICESugarProMinimal$delayedInit$body.apply(ICESugarProMinimal.scala:350)
[error]         at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error]         at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error]         at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]         at scala.App$$anonfun$main$1.apply(App.scala:76)
[error]         at scala.collection.immutable.List.foreach(List.scala:392)
[error]         at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error]         at scala.App$class.main(App.scala:76)
[error]         at saxon.board.muselab.ICESugarPro.ICESugarProMinimal$.main(ICESugarProMinimal.scala:350)
[error]         at saxon.board.muselab.ICESugarPro.ICESugarProMinimal.main(ICESugarProMinimal.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 10 s, completed 2021/10/12 6:49:16

ICESugarProMinimal.scala with errors

I guess this means I'm missing something, but is there any other code that can help me understand DMA on the bmb bus?

Dolu1990 commented 3 years ago

Hi,

So, in your settings, the DMA never use the linked list of descriptor feature (scatter-gatter), so you should remove all the lines which have reference to readSg and writeSg in your toplevel, then it should be fine ^^

Explenation : system_dma_readSg_masterModel_accessRequirements system_dma_writeSg_masterModel_accessRequirements

=> both bus where specified in the interconnect, but not implemented by the DmaSgGenerator

jmio commented 3 years ago

Thank you. It worked (^^)