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SpinalHDL / SaxonSoc

SoC based on VexRiscv and ICE40 UP5K
MIT License
147 stars 40 forks source link

Support for Xyloni #74

Closed surabibio closed 2 years ago

surabibio commented 2 years ago

Xyloni is a low cost demo board from Efinix. Efinix devices are the only readily available FPGA in market to the common engineer (June 2022) As engineers migrate to Efinix from vendor dependent designs (like designs in AHDL, designs that use proprietary modules, proprietary SoC like Nios ) SpinalHDL and SaxonSoc is a God sent savior. A solid reference code in SpinalHDL is the need of the hour.

Dolu1990 commented 2 years ago

Hi ^^

Sorry i was quite busy those last days, my emails / notification start to pile up quite a bit too much XD

So, the only thing which isn't ok in the PR are the following files : hardware/synthesis/efinix/xyloni/a_verilog/SoC.v hardware/synthesis/efinix/xyloni/a_verilog/SoC.v.xxx.bin

The issue is that those are big generated ones, which are kind of too big to be keept in a git history. Would it be possible instead to have the generation command documented (generating into hardware/netlist), and having the synthesis scripts using them there ?

Else all good :) Thanks

surabibio commented 2 years ago

Hi Charles, Removed the generated files and given instructions in the readme.md file on how to go about the flow.

Dolu1990 commented 2 years ago

Thanks ^^