Open numero-744 opened 2 years ago
that would be great if there are SpinalHDL/Verilog/SystemVerilog/VHDL,user can easily compare and study by that.
However, it's necessary to make that happen.
---Original--- From: @.> Date: Thu, Nov 17, 2022 00:29 AM To: @.>; Cc: @.**@.>; Subject: Re: [SpinalHDL/SpinalDoc-RTD] equivalent constructs at elaborationtime/hardware/sim (Issue #145)
@Readon
What do you think of this?
Maybe do the same thing for VHDL vs SystemVerilog vs SpinalHDL?
— Reply to this email directly, view it on GitHub, or unsubscribe. You are receiving this because you were mentioned.Message ID: @.***>
However, it's necessary to make that happen.
@Readon I'm focusing on RTD for the next 2 weeks, we'll see what it gives ^^
I wanted a big rework of RTD, I have started this morning. I'm waiting for other PRs to be merged (automated code checks and pdf generation in GH workflow) before I publish a PR.
After this I'll address RTD issues like this one.
Can be fancy :D
@Readon
What do you think of this?
https://sublime-and-sphinx-guide.readthedocs.io/en/latest/code_blocks.html#code-examples-in-multiple-languages
Maybe do the same thing for VHDL vs SystemVerilog vs SpinalHDL?