Open digee-bytes opened 3 months ago
Hi, The SpinalHDL system verilog backend is mostly the same than the verilog one, with very minor differences.
Are you thinking about things as System verilog interface ?
Yes, features like interfaces and support for UVM and complete verification flow such things
ahhh so, SpinalHDL doesn't generate system verilog interface, the difference in generation is mostly in how assertion are emited
Just like the VHDL or Verilog Generation, does SpinalHDL generate SystemVerilog codes and needs some basic info about using the verification environment in SpinalHDL?