SpinalHDL / SpinalDoc-RTD

The sources of the online SpinalHDL doc
https://spinalhdl.github.io/SpinalDoc-RTD/
Creative Commons Zero v1.0 Universal
25 stars 61 forks source link

SystemVerilog Support #264

Open digee-bytes opened 3 months ago

digee-bytes commented 3 months ago

Just like the VHDL or Verilog Generation, does SpinalHDL generate SystemVerilog codes and needs some basic info about using the verification environment in SpinalHDL?

Dolu1990 commented 3 months ago

Hi, The SpinalHDL system verilog backend is mostly the same than the verilog one, with very minor differences.

Are you thinking about things as System verilog interface ?

digee-bytes commented 3 months ago

Yes, features like interfaces and support for UVM and complete verification flow such things

Dolu1990 commented 3 months ago

ahhh so, SpinalHDL doesn't generate system verilog interface, the difference in generation is mostly in how assertion are emited