SystemVerilog Support

[digee-bytes]

Just like the VHDL or Verilog Generation, does SpinalHDL generate SystemVerilog codes and needs some basic info about using the verification environment in SpinalHDL?

[Dolu1990]

Hi, The SpinalHDL system verilog backend is mostly the same than the verilog one, with very minor differences.

Are you thinking about things as System verilog interface ?

[digee-bytes]

Yes, features like interfaces and support for UVM and complete verification flow such things

[Dolu1990]

ahhh so, SpinalHDL doesn't generate system verilog interface, the difference in generation is mostly in how assertion are emited