Verilator simulation should not exit if severity is not `FAILURE`

[goekce]

case class Dut() extends Component {
  val io = new Bundle {
    val i = in Bool()
    val o = out Bool()
  }
  io.o := io.i
}
object Test extends App {
  Config.sim.compile(Dut()).doSim { dut =>
    dut.clockDomain.forkStimulus(period = 10)
      dut.clockDomain.waitRisingEdge()
      assert(dut.io.i.toBoolean != dut.io.o.toBoolean, WARNING)
      dut.clockDomain.waitRisingEdge()
      dut.clockDomain.waitRisingEdge()
  }
}

sbt "runMain Test"

Output

...
[info] [Progress] Verilator compilation started
[info] [info] Found cached verilator binaries
[info] [Progress] Verilator compilation done in 483.369 ms
[info] [Progress] Start Dut test simulation with seed 469730164
[info] [Error] Simulation failed at time=170
[error] Exception in thread "main" java.lang.AssertionError: assertion failed: spinal.core.WARNING$@e394c64
...
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
...

The simulation exits immediately at 170. I would expect the simulation to continue until the simulation code's end.

According to the docs:

* - NOTE
     - Used to report an informative message
   * - WARNING
     - Used to report an unusual case
   * - ERROR
     - Used to report an situation that should not happen
   * - FAILURE
     - Used to report a fatal situation and close the simulation

I understand that only FAILURE should close the simulation, not the other severities.

I use Verilator 5.028 2024-08-21

[Readon]

To my knowledge, the assert would raise an error while the equation test failed. If you just want to log the inequality, do not use assert, may be log utility is a good alternative.