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SpinalHDL / SpinalHDL

Scala based HDL
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Assert AxiLite4BusInterface addresses do not exceed mapping size #848

Open Readon opened 2 years ago

Readon commented 2 years ago

For example, when bus interface initiated as below

val busif = Apb3BusInterface(io.apb,(0x0000, 100 Byte)

Then if the following newReg would cause an address overflow is not reported now. However, the overall usage of the address space is always important for a designer. Otherwise, why is the '100Byte' in the above code necessary?

Dolu1990 commented 2 years ago

Sound good to me ^^

Readon commented 1 year ago

I think it would be fixed by #976