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SpinalHDL / SpinalWorkshop

Labs to learn SpinalHDL
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Is there an error in uart/assets/diagram.png? #20

Closed LurenAA closed 1 year ago

LurenAA commented 1 year ago

image image

Should io.samplingTick also be connected to the enable terminals of the two previous D Flip-Flop? the code is in File：uart/UartCtrlRx.scala thank you

Dolu1990 commented 1 year ago

Hi, ahhh the diagram doesn't match the implémentation you are right. So i would say idealy, the History range should be 0 until samplingSize, and the 2 first flip flop should be made via a BufferCC to avoid introducing that inecessary latency (while keeping the metastability protection)

LurenAA commented 1 year ago

thank you