blackboxAndClock

[ICJJ]

Q1:

when i point the dump depth with verilator

  def apply() = SimConfig.withConfig(SpinalConfig(targetDirectory = "rtl").dumpWave(0, "./mem.vcd"))

and no waves generated. The sim reports as follow:

-Info: /mnt/hgfs/virtual_share/cjj/spinal/SpinalWorkshop/./simWorkspace/tmp/job_1/MemorySumming.v:88: $dumpvar ignored, as Verilated without --trace

Q2:

how to point the dump depth with hier? The second var in dumpvar().

[Dolu1990]

SpinalConfig.dumpWave(0, "./mem.vcd") is about how the verilog is generated, but it doesn't interract with SpinalSim i would say, i'm not sure verilator use the verilog to figure out how to trace things.

You need to do SimConfig.withWave.... instead

how to point the dump depth with hier?

Not implemented so far, it juste trace everything

[ICJJ]

You need to do SimConfig.withWave.... instead The SpinalConfig.dumpWave(0, "./mem.vcd") not for verilator tool to dump wave vpi. I use withWave, and even use withWaveDepth to mark the dump depth. compiled = SimConfig.withWave.withWaveDepth(1).withConfig( SpinalConfig(targetDirectory = "rtl")).addRtl("rtl/Ram_1w_1r_2c.v").compile( MemorySumming( writeClock = ClockDomain.external("io_wr", withReset = false), sumClock = ClockDomain.external("io_sum") ) ) But the wave.vcd still dump TOP scope.

$scope module TOP $end
$var wire  1 0 clk $end
$var wire  1 / io_sum_clk $end
$var wire  1 , io_sum_done $end
$var wire  1 2 io_sum_reset $end
$var wire  1 + io_sum_start $end
$var wire 16 - io_sum_value [15:0] $end
$var wire  8 ) io_wr_addr [7:0] $end
$var wire  1 . io_wr_clk $end
$var wire 16 * io_wr_data [15:0] $end
$var wire  1 ( io_wr_en $end
$var wire  1 1 reset $end
$scope module MemorySumming $end
$var wire  1 0 clk $end
$var wire  1 / io_sum_clk $end
$var wire  1 , io_sum_done $end

I want to dump rtl top scope(MemorySumming) wave data for better debug with rtl verilog

[Dolu1990]

I tried :

  SimConfig.withWave.compile(new Component{
    val x = slave Stream(UInt(8 bits))
    val y = master Stream(UInt(8 bits))

    x.queue(4) >> y // the queue function create a fifo module 
  }).doSim{dut =>
    sleep(10)
  }

It gives me full visibility :

 $scope module TOP $end
  $var wire  1 ? clk $end
  $var wire  1 @ reset $end
  $var wire  8 ; x_payload [7:0] $end
  $var wire  1 : x_ready $end
  $var wire  1 9 x_valid $end
  $var wire  8 > y_payload [7:0] $end
  $var wire  1 = y_ready $end
  $var wire  1 < y_valid $end
  $scope module unamed $end
   $var wire  1 ? clk $end
   $var wire  1 @ reset $end
   $var wire  3 B x_fifo_io_availability [2:0] $end
   $var wire  3 A x_fifo_io_occupancy [2:0] $end
   $var wire  8 ' x_fifo_io_pop_payload [7:0] $end
   $var wire  1 # x_fifo_io_pop_valid $end
   $var wire  1 1 x_fifo_io_push_ready $end
   $var wire  8 ; x_payload [7:0] $end
   $var wire  1 : x_ready $end
   $var wire  1 9 x_valid $end
   $var wire  8 > y_payload [7:0] $end
   $var wire  1 = y_ready $end
   $var wire  1 < y_valid $end
   $scope module x_fifo $end
    $var wire  1 ? clk $end
    $var wire  3 B io_availability [2:0] $end
    $var wire  1 D io_flush $end
    $var wire  3 A io_occupancy [2:0] $end
    $var wire  8 ' io_pop_payload [7:0] $end
    $var wire  1 = io_pop_ready $end
    $var wire  1 # io_pop_valid $end
    $var wire  1 - io_push_fire $end

Isn't it what you want ? (all modules being in the wave

[ICJJ]

I tried :

  SimConfig.withWave.compile(new Component{
    val x = slave Stream(UInt(8 bits))
    val y = master Stream(UInt(8 bits))

    x.queue(4) >> y // the queue function create a fifo module 
  }).doSim{dut =>
    sleep(10)
  }

It gives me full visibility :

 $scope module TOP $end
  $var wire  1 ? clk $end
  $var wire  1 @ reset $end
  $var wire  8 ; x_payload [7:0] $end
  $var wire  1 : x_ready $end
  $var wire  1 9 x_valid $end
  $var wire  8 > y_payload [7:0] $end
  $var wire  1 = y_ready $end
  $var wire  1 < y_valid $end
  $scope module unamed $end
   $var wire  1 ? clk $end
   $var wire  1 @ reset $end
   $var wire  3 B x_fifo_io_availability [2:0] $end
   $var wire  3 A x_fifo_io_occupancy [2:0] $end
   $var wire  8 ' x_fifo_io_pop_payload [7:0] $end
   $var wire  1 # x_fifo_io_pop_valid $end
   $var wire  1 1 x_fifo_io_push_ready $end
   $var wire  8 ; x_payload [7:0] $end
   $var wire  1 : x_ready $end
   $var wire  1 9 x_valid $end
   $var wire  8 > y_payload [7:0] $end
   $var wire  1 = y_ready $end
   $var wire  1 < y_valid $end
   $scope module x_fifo $end
    $var wire  1 ? clk $end
    $var wire  3 B io_availability [2:0] $end
    $var wire  1 D io_flush $end
    $var wire  3 A io_occupancy [2:0] $end
    $var wire  8 ' io_pop_payload [7:0] $end
    $var wire  1 = io_pop_ready $end
    $var wire  1 # io_pop_valid $end
    $var wire  1 - io_push_fire $end

Isn't it what you want ? (all modules being in the wave

Thanks for your try. But this is not my want.What the vcd file of my want is only include rtl and not include TOP scope. Vcd file like this:

(without TOP scope)
  $scope module DemoFifo $end
   $var wire  1 < clk $end
   $var wire  1 = reset $end
   $var wire  3 * x_fifo_io_availability [2:0] $end
   $var wire  3 ) x_fifo_io_occupancy [2:0] $end
   $var wire  8 ; x_fifo_io_pop_payload [7:0] $end
   $var wire  1 9 x_fifo_io_pop_valid $end
   $var wire  1 7 x_fifo_io_push_ready $end
   $var wire  8 8 x_payload [7:0] $end
   $var wire  1 7 x_ready $end
   $var wire  1 6 x_valid $end
   $var wire  8 ; y_payload [7:0] $end
   $var wire  1 : y_ready $end
   $var wire  1 9 y_valid $end
   $scope module x_fifo $end
    $var wire  1 < clk $end
...

Because the spinalhdl not generate verilog include Top module. When i user the verdi or other wave debug tool to open fsdb file(transverse from vcd) and verilog file, and a error will come out with drop signal to wave window from code window.

[Dolu1990]

Ahhh i see. Hmm i don't know then, not sure if Verilator can be configured for this.

The only workaround i know (in terms of flow) is to use GTKwave to look at the wave. Also instead of "withWave", to use "withFstWave" that produce a compresed waveform which is much better to use. But all of this may not fit your use case.