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SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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UserInterruptPlugin Interrupt Enable Problem #142

Open cxzzzz opened 4 years ago

cxzzzz commented 4 years ago

hi, i notice that when adding a user-defined interrupt using UserInterruptPlugin, it just use the interruptPending as the cond signal ,without any enable signal as a gate controller https://github.com/SpinalHDL/VexRiscv/blob/98de02051e1a5c9400c022dc61acd4bd0507f8a5/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L1153-L1155

it seems some other interrupts useenable && pending as addInterupt function's cond : https://github.com/SpinalHDL/VexRiscv/blob/98de02051e1a5c9400c022dc61acd4bd0507f8a5/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L690-L692 Is it necessary to do the same for user-defined interrupts ( csr.addInterrupt(interruptPending && interruptEnable , code, privilege, Nil) ?

Dolu1990 commented 4 years ago

Hi,

Hoo nice catch, csr.addInterrupt(interruptPending , code, privilege, Nil) is missing the interruptEnable condition int he UserInterruptPlugin.

I pushed the fix in dev

Is it necessary to do the same for user-defined interrupts ( csr.addInterrupt(interruptPending && interruptEnable , code, privilege, Nil) ?

It isn't realy necesary to use the interruptEnable, but better as it follow the RISC-V way of doing things.