search

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
2.5k stars 417 forks source link

Briey SoC simulation hang at beginning #216

Open Flywing2018 opened 3 years ago

Flywing2018 commented 3 years ago

Hi, I follow the README to config/build/run verilator simulation for Briey SoC. The VGA window prompted. However, it displays nothing, terminal print 2 lines below then no output any more. Briey

Flywing2018 commented 3 years ago

BTW, I have try this flow both on Ubuntu20.04 and RHEL8, the result are same. Does the Briey SoC flow miss something in README or I miss some important step?

Dolu1990 commented 3 years ago

Hi, i think it is normal, you need to load some binaries into the simulation, you can do it by connecting openocd and gdb to it (the sdram is blank when the sim boot, and there is no bootloader in the onchip ram)