search

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
2.49k stars 416 forks source link

can't capture full CL output of "make run" for Briey #232

Open henryrgithub opened 2 years ago

henryrgithub commented 2 years ago

Hello,

I'm working on getting started with VexRiscv. I can successfully run Briey and interact with it via OpenOCD and GDB.

However, in trying to build some automation tools, I've noticed that I can't capture some of its output. When I run

`VexRiscv/src/test/cpp/briey/obj_dir$ ./VBriey

I get

BOOT SDRAM : MODE REGISTER DEFINITION CAS=3 burstLength=0 in return, whereas when I run

VexRiscv/src/test/cpp/briey/obj_dir$ ./VBriey > log.txt

all I get is an empty text file. Similarly if I "make clean run" from one folder up, I can log the build process, but the log is still missing the boot and SDRAM lines. Now, I can work around the lack of these lines, but it would require going through the build process each time and wouldn't be as elegant.

Any tips on why I can't capture the BOOT and SDRAM lines?

Dolu1990 commented 2 years ago

Hi,

I have no idea why "./VBriey > log.txt" isn't working. Maybe can try to dump away some of the simulation main and add some printf to see until which point things are back to normal ?