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SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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data cache stuck #264

Open hchoi-lattice opened 2 years ago

hchoi-lattice commented 2 years ago

Hi Dolu1990, Found a weird D-cache stuck issue. Attached the waveform. It's related to refilling. D-cache goes into line fill phase and expect loader_counter_values to go up. On the other hand, dBus_cmd_valid is not asserted and it prevents main_cpu_dbus_cyc from being asserted. So, external memory controller does not know that it needs to send data to D-cache, while D-cache is waiting for the data. This makes a deadlock. Interestingly, the old version of VexRiscv (Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8) does not have this issue and works well. Thanks, Hoon

waveform

Dolu1990 commented 2 years ago

Hi ^^ Weird, would there be a way for me to get the wave file of the case ? That would realy help :D

hchoi-lattice commented 2 years ago

Confirmed that the same issue was reported and already solved in Linefill Question #170. Thanks!

Dolu1990 commented 2 years ago

Hoo so with upstream version of VexRiscv, everything is good on your side ?