Open Light9162 opened 1 year ago
Hi, the pure VexRiscv synthesis number are with FPGA with many many pins and without the SoC infrastructure : https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/SynthesisBench.scala
If you want a SoC, you can check Murax / Briey, which have everything for a standalone SoC.
Hello! @Dolu1990, I know you previously answered a similar question on issue #22. I running into the same error on the DE1-SOC which uses a Cyclone V chip. My confusion comes from the fact that you have benchmark numbers for the full chip on Cyclone V so I would think it would work out of the box no? Should I try to cut GPIO pins from the design also? What file do you suggested I edit to do that?
Thank you in advanced!