SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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Questions about the memory of the Murax SoC and the VexRiscv in general #339

Closed joeljeanmonod-rgb closed 1 year ago

joeljeanmonod-rgb commented 1 year ago

Hi,

I have a few questions about how the memory map work with Murax Soc and the VexRiscv in general.

My first question is about how the processor starts. Of what i understand the sequence is as follow :

  1. Start at the adress of the resetVector = 0x80000000l
  2. Read the instructions of the crt.S which are at the adress 0x80000000l
  3. The crt.S enable the interrupts for the timer and the uart and then jump to the main function
  4. Start the the main function in the main.c

is that correct ?

My second question is about the memory map. I have a few questions about it :

  1. Is the processor using a part of the memory map for internal use ?
  2. if yes, where can i find the memory map of the processor for internal use ?
  3. if no, does that mean that the memory map entirely available for the user ? Can for exemple put the RAM at the adress 0x00000000l directly with the resetVector = 0x00000000l ?

thanks in advance for your response.

Dolu1990 commented 1 year ago

HI ^^

The crt.S enable the interrupts for the timer and the uart and then jump to the main function

Not exactly, it enable timer and external interrupts in the core, the uart interrupt is connected to a interrupt controller which goes to that external interrupt.

Is the processor using a part of the memory map for internal use ?

No

if no, does that mean that the memory map entirely available for the user ?

Yes

Can for exemple put the RAM at the adress 0x00000000l directly with the resetVector = 0x00000000l ?

Yes, but overall i would say the best is to put nothing at 0x00000000 (so null pointer access will not access memory)

joeljeanmonod-rgb commented 1 year ago

Thank you so much