SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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SIMD_ADD custom instruction not working in C code #349

Closed tiagoasilva-meec closed 1 year ago

tiagoasilva-meec commented 1 year ago

I was thinking about implementing a custom instruction in VexRiscv, so I decided to try the SimdAddPlugin example first.

I inserted the SimdAddPlugin in my configuration list and generated the verilog code. I was using the following macros to call the custom instruction from my C code (I have these in a .S file actually):

define SIMD_ADD(_rd, _rs1, _rs2) \

R_TYPEINSTR(0b0000011, reg ## rs2, reg ## rs1, 0b000, reg ## _rd, 0b0001011)

define R_TYPE_INSTR(_f7, _rs2, _rs1, _f3, _rd, _opc) \

.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | (_opc))

I can't get anything by calling SIMD_ADD from main, in my C code. It doesn't execute or return anything. However, I tryed changing the arguments and opcode of the R_TYPE_INSTR macro and I could execute several riscv instructions (ADD, SUB, SLT, XOR, etc), already implemented. So the problem may be related with the SimdAddPlugin or something else missing. It don't think it has to do with the macros.

Dolu1990 commented 1 year ago

Hi,

I just tried to run : https://github.com/SpinalHDL/VexRiscv#add-a-custom-instruction-to-the-cpu-via-the-plugin-system

# Generate the CPU
sbt "runMain vexriscv.demo.GenCustomSimdAdd"

cd src/test/cpp/regression/

# Optionally add TRACE=yes if you want to get the VCD waveform from the simulation.
# Also you have to know that, by default, the testbench introduce instruction/data bus stall.
# Note the CUSTOM_SIMD_ADD flag is set to yes.
make clean run IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no DHRYSTONE=no REDO=1 CUSTOM_SIMD_ADD=yes

All seems good.

Can you send your application.elf ? or assembly ?