Open likewise opened 1 year ago
the verilator testbench of VexRiscv alone doesn't implement JTAG, but some more direct connections. So openocd get confused as it doesn't know about it.
You can ignore all the JTAG related error it throws at you ^^
My origin problem is that dev
branches show regressions on my hardware, i.e. I cannot debug my VexRiscv software anymore.
I was hoping I could replicate the problem in simulation.
How should I try to debug this regression in simulation?
Ahhh, then you can use the MuraxSim (SpinalSim), See : https://github.com/SpinalHDL/VexRiscv#murax-soc
This virtualize a proper jtag. Hardware issue should be reproducable there aswell.
What kind of regression exactly do you get on your hardware ?
Currently I am developing against a local SpinalHDL
dev
branch, along with local VexRiscvdev
and the VexRiscv-specific latest OpenOCD (i.e. using the "old" VexRiscv debug module") and I am seeing a possible regression during working with OpenOCD on my hardware. I am investigating. So I went back to VexRiscv/Sim/OpenOCD as per the README.In simulation, I get different errors starting OpenOCD, but things do seem to work. But I do see errors I never saw before, are the following errors innocent?
This is the set of sources (current tips of
dev
,dev
, riscv-spinal` branches, in this order) for:I am following the
README.md
: