search

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
2.52k stars 420 forks source link

RiscV Counters #361

Open jjjt-git opened 1 year ago

jjjt-git commented 1 year ago

Since I need them for a project, I was wondering, if the performance counters will be implemented. I might try building them myself, but I feel not as familiar with either Spinal or VexRiscv yet.

Dolu1990 commented 1 year ago

Personnaly, it isn't my plan to implement them, i'm very busy on other things, but i'm happy to merge PR :)

but I feel not as familiar with either Spinal or VexRiscv yet.

I understand the difficulty