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SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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Perf counters #388

Closed jjjt-git closed 8 months ago

jjjt-git commented 10 months ago

Fixes #361 Not tested, because I did not find the time for it. So I do not know, whether it works or not.

Dolu1990 commented 10 months ago

Hi,

One thing would be to preserve backward compatibility, i mean in particualr the mcycleAccess = CsrAccess.NONE, and others.

Idea being to preserve that feature there, while also havig the possibility to have it implemented by your plugin :)

jjjt-git commented 10 months ago

I added the legacy counters back in, but made sure, they will not be generated if a CounterService is part of the pipeline. I still have not tested the CounterPlugin, but hope to get to that later that week...

Dolu1990 commented 10 months ago

Ok thanks :)

jjjt-git commented 9 months ago

The Plugin works.

jjjt-git commented 8 months ago

I reverted the removal of the config options. The GenFull still uses the CounterPlugin, as does the VexRiscvAxi4LinuxPlicClint. However there is (currently) no module in the repo to provide performance counters. It should be quite simple to add to the various cache-modules, but I have not looked into it yet.

Dolu1990 commented 8 months ago

Thanks ^^ The pr seems all good to me, i just updated it to go into dev instead of master.

Also note since november i'm working on VexiiRiscv : https://github.com/SpinalHDL/VexiiRiscv

medium / long terms the idea is to migrate toward it. Let's me know if you are interrested into the project ^^

jjjt-git commented 8 months ago

Fixed the condition.

Dolu1990 commented 8 months ago

Thanks ^^

jjjt-git commented 8 months ago

my pleasure