SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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Exit cycle accurate simulation #398

Closed ashuthosh-mr closed 1 week ago

ashuthosh-mr commented 8 months ago

Hi,

Is there a way to exit the verilator simulation from the C code whose hex is getting executed using RUN_HEX. For some reason, certain C codes are exiting but others are not. I do not know the exact reason why it executes all instructions and gets stuck at the end of main. By default (hello_world), it falls in infinite loop. But on changing crt.S to include

li x2, 0xF00FFF20
sw x0, 0(x2)

few codes come out of simulation, printing cycles. But as I mentioned this fix didn't work for certain C codes. Is there a way to exit simulation through C code?

Thank you

Dolu1990 commented 8 months ago

Hi,

For some reason, if you the debug plugin is enabled, those exit condition are disabled : https://github.com/SpinalHDL/VexRiscv/blob/6aeb6d4d4348b201fcc8403764ffa3a05ba48fc8/src/test/cpp/regression/main.cpp#L1970

Try removing the #ifndef