GDB not working with FPGA

albaEDA commented 7 years ago

Hello all, I'm having a little problem with the FPGA implementation to test functionality on sillicon and the compilation is completely fine but when it comes to interfacing with the board. The OpenOCD can connect, I'm using the command:

openocd -f tcl/interface/altera-usb-blaster.cfg -c "set BRIEY_CPU0_YAML /home/aaron/VexRiscv/cpu0.yaml" -f tcl/target/briey.cfg

However, when then trying to connect to the GDB with:

target remote localhost:3333

It times out, am I missing something? I'm using the DE0-nano development board.

Dolu1990 commented 7 years ago

Hi,

How do you have linked the Altera USB blaster to the briey toplevel ? (Currently I always have used a dedicated JTAG via some USB FTDI)

Also about the DE0-nano, i already have test Briey on it, be carefull the SDRAM configuration is different than the default one (DE1-SoC). You need to generate the toplevel via (for instance) this main : https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/Briey.scala#L394

albaEDA commented 7 years ago

I have used the default:

io_jtag_tck => GPIO_2(0), io_jtag_tms => GPIO_2(3), io_jtag_tdi => GPIO_2(1), io_jtag_tdo => GPIO_2(2),

Then attached the correct slots on the blaster but it gets to:

YOLO riscv_spinal_target_create Info : set servers polling period to 50ms YOLO riscv_spinal_init_target Info : No lowlevel driver configured, will try them all Info : Altera USB-Blaster II found (Firm. rev. = 6�l) Info : This adapter doesn't support configurable speed

and stops and I cannot connect to it via GDB. What sort of FTDI chip/setup did you use. I think it would be helpful if I tried it your way, since you have already tested it.

Dolu1990 commented 7 years ago

I'm using the ft2232h chip, so, the very "standard" way, the only element on the jtag chain is the Briey SOC. Do you have multiple jtag tap on your JTAG ? Or the Briey is the only one ? Have you powered the vcc_trgt pin of the dongle ? (i had forget it many times XD) Also could you give a try with the verbose openocd ? -v3 if i remember it right

Dolu1990 commented 7 years ago

Also, just to minimise risks of error, don't modify any thing of the de0-nano project/sources (for the moment :)) Just for sanity, until this first step work

albaEDA commented 7 years ago

I'll run through my setup, because I may have just made a wiring mistake!

So I tried ordering in the ft232h breakout board form adafruit:

https://www.adafruit.com/product/2264

Reverted back into a clean DE0-nano file from here:

https://drive.google.com/drive/folders/0B-CqLXDTaMbKZGdJZlZ5THAxRTQ?usp=sharing

Then I looked at the top level files for the JTAG and it seems like they are on:

  io_jtag_tck =>  GPIO_2(0),
  io_jtag_tms =>  GPIO_2(3),
  io_jtag_tdi =>  GPIO_2(1),
  io_jtag_tdo =>  GPIO_2(2),

Then looking at the pin mapping it shows:

GPIO_2[0] | PIN_A14 GPIO_2[1] | PIN_B16 GPIO_2[2] | PIN_C14 GPIO_2[3] | PIN_C16

So looking at the pin mapping of the DE0 nano:

Then looking in the FT232H datasheet it shows

Pin | MPSSE Configuration Description 13 | JTAG TCK, Test interface clock 14 | JTAG TDI, Test Data Input 15 | JTAG TDO, Test Data output 16 | JTAG TMS, Test Mode Select

with pins 13, 14, 15, 16, 17, 18, 19, 20 on the ADBUS[7:0] and from adafruit:

D0 through D7 - These are the ADBUS pins

So my final wiring is:

13 (D0) -> A14 14 (D1) -> B16 15 (D2) -> C14 16 (D3) -> C16

Then I got the OpenOCD from

https://github.com/SpinalHDL/openocd_riscv

Compiled it ran it with the simulation okay, then I tried running; $ sudo openocd -f tcl/interface/ftdi/ft2232h_breakout.cfg -c 'set BRIEY_CPU0_YAML /home/aaron/VexRis/cpu0.yaml' -f tcl/target/briey.cfg Got an error that it wasn't found so changed ft2232h_breakout.cfg to

interface ftdi
#ftdi_device_desc "FT2232H Breakout Module"
ftdi_vid_pid 0x0403 0x6014

# Channel for using JTAG
ftdi_channel 0

# Initial state and direction setting (ref. AN_135_MPSSE_Basics.pdf)
# ftdi_layout_init [data] [direction]

#  name   signal  state      direction  JTAG name
# *DBUS0  TCK/SK  (low =0)   (out=1)    TDI
# *DBUS1  TDI/DO  (low =0)   (out=1)    TDO
# *DBUS2  TDO/DI  (low =0)   (in =0)    TCK
# *DBUS3  TMS/CS  (high=1)   (out=1)    TMS
# *DBUS4  GPIOL0  (low =0)   (out=0)    (nTRST)
# *DBUS5  GPIOL1  (low =0)   (out=0)    WAIT | STOPCLK
# *DBUS6  GPIOL2  (low =0)   (out=0)    (nRST)
# *DBUS7  GPIOL3  (low =0)   (out=0)    RTCK
ftdi_layout_init 0xfff8 0xfffb
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200

Ran the OpenOCD again and got the following error;

$sudo openocd -d -f tcl/interface/ftdi/ft2232h_breakout.cfg -c 'set BRIEY_CPU0_YAML /home/aaron/VexRiscv/cpu0.yaml' -f tcl/target/briey.cfg

Open On-Chip Debugger 0.10.0+dev-00292-g14dcabd (2017-10-07-14:13)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
User : 13 1 command.c:544 command_print(): debug_level: 3
Debug: 14 2 options.c:181 add_default_dirs(): bindir=/usr/local/bin
Debug: 15 2 options.c:182 add_default_dirs(): pkgdatadir=/usr/local/share/openocd
Debug: 16 2 options.c:183 add_default_dirs(): exepath=/usr/local/bin
Debug: 17 2 options.c:184 add_default_dirs(): bin2data=../share/openocd
Debug: 18 2 configuration.c:42 add_script_search_dir(): adding /home/aaron/.openocd
Debug: 19 2 configuration.c:42 add_script_search_dir(): adding /usr/local/bin/../share/openocd/site
Debug: 20 2 configuration.c:42 add_script_search_dir(): adding /usr/local/bin/../share/openocd/scripts
Debug: 21 2 configuration.c:82 find_file(): found tcl/interface/ftdi/ft2232h_breakout.cfg
Debug: 22 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_interface ftdi
Debug: 23 2 command.c:143 script_debug(): command - interface ocd_interface ftdi
Debug: 25 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_device_desc'...
Debug: 26 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_serial'...
Debug: 27 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_location'...
Debug: 28 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_channel'...
Debug: 29 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_layout_init'...
Debug: 30 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_layout_signal'...
Debug: 31 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_set_signal'...
Debug: 32 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_get_signal'...
Debug: 33 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_vid_pid'...
Debug: 34 2 command.c:364 register_command_handler(): registering 'ocd_ftdi_tdo_sample_edge'...
Debug: 35 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_vid_pid 0x0403 0x6014
Debug: 36 2 command.c:143 script_debug(): command - ftdi_vid_pid ocd_ftdi_vid_pid 0x0403 0x6014
Debug: 38 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_channel 0
Debug: 39 2 command.c:143 script_debug(): command - ftdi_channel ocd_ftdi_channel 0
Debug: 41 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_init 0xfff8 0xfffb
Debug: 42 2 command.c:143 script_debug(): command - ftdi_layout_init ocd_ftdi_layout_init 0xfff8 0xfffb
Debug: 44 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
Debug: 45 2 command.c:143 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
Debug: 47 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200
Debug: 48 2 command.c:143 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200
User : 50 2 command.c:675 command_run_line(): /home/aaron/VexRiscv/cpu0.yamlUser : 51 2 command.c:677 command_run_line(): 
Debug: 52 2 configuration.c:82 find_file(): found tcl/target/briey.cfg
Debug: 53 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 50
Debug: 54 2 command.c:143 script_debug(): command - adapter_khz ocd_adapter_khz 50
Debug: 56 2 core.c:1631 jtag_config_khz(): handle jtag khz
Debug: 57 2 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 58 2 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
User : 59 2 command.c:544 command_print(): adapter speed: 50 kHz
Debug: 60 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_adapter_nsrst_delay 260
Debug: 61 2 command.c:143 script_debug(): command - adapter_nsrst_delay ocd_adapter_nsrst_delay 260
User : 63 2 command.c:544 command_print(): adapter_nsrst_delay: 260
Debug: 64 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 65 2 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Info : 66 2 transport.c:286 jim_transport_select(): auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Debug: 67 2 command.c:364 register_command_handler(): registering 'ocd_jtag_flush_queue_sleep'...
Debug: 68 2 command.c:364 register_command_handler(): registering 'ocd_jtag_rclk'...
Debug: 69 2 command.c:364 register_command_handler(): registering 'ocd_jtag_ntrst_delay'...
Debug: 70 2 command.c:364 register_command_handler(): registering 'ocd_jtag_ntrst_assert_width'...
Debug: 71 2 command.c:364 register_command_handler(): registering 'ocd_scan_chain'...
Debug: 72 2 command.c:364 register_command_handler(): registering 'ocd_jtag_reset'...
Debug: 73 2 command.c:364 register_command_handler(): registering 'ocd_runtest'...
Debug: 74 3 command.c:364 register_command_handler(): registering 'ocd_irscan'...
Debug: 75 3 command.c:364 register_command_handler(): registering 'ocd_verify_ircapture'...
Debug: 76 3 command.c:364 register_command_handler(): registering 'ocd_verify_jtag'...
Debug: 77 3 command.c:364 register_command_handler(): registering 'ocd_tms_sequence'...
Debug: 78 3 command.c:364 register_command_handler(): registering 'ocd_wait_srst_deassert'...
Debug: 79 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 80 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 81 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 82 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 83 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 84 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 85 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 86 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 87 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 88 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 89 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 90 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 91 3 command.c:364 register_command_handler(): registering 'ocd_jtag'...
Debug: 92 3 command.c:364 register_command_handler(): registering 'ocd_svf'...
Debug: 93 3 command.c:364 register_command_handler(): registering 'ocd_xsvf'...
Debug: 94 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 95 3 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 96 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag_ntrst_delay 250
Debug: 97 3 command.c:143 script_debug(): command - jtag_ntrst_delay ocd_jtag_ntrst_delay 250
User : 99 3 command.c:544 command_print(): jtag_ntrst_delay: 250
Debug: 100 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag newtap fpga_spinal bridge -expected-id 0x10001fff -irlen 4 -ircapture 0x1 -irmask 0xF
Debug: 101 3 command.c:143 script_debug(): command - ocd_jtag ocd_jtag newtap fpga_spinal bridge -expected-id 0x10001fff -irlen 4 -ircapture 0x1 -irmask 0xF
Debug: 102 3 tcl.c:549 jim_newtap_cmd(): Creating New Tap, Chip: fpga_spinal, Tap: bridge, Dotted: fpga_spinal.bridge, 8 params
Debug: 103 3 tcl.c:573 jim_newtap_cmd(): Processing option: -expected-id
Debug: 104 3 tcl.c:573 jim_newtap_cmd(): Processing option: -irlen
Debug: 105 3 tcl.c:573 jim_newtap_cmd(): Processing option: -ircapture
Debug: 106 3 tcl.c:573 jim_newtap_cmd(): Processing option: -irmask
Debug: 107 3 core.c:1304 jtag_tap_init(): Created Tap: fpga_spinal.bridge @ abs position 0, irlen 4, capture: 0x1 mask: 0xf
Debug: 108 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target create fpga_spinal.cpu0 vexriscv -endian little -chain-position fpga_spinal.bridge -coreid 0 -dbgbase 0xF00F0000
Debug: 109 3 command.c:143 script_debug(): command - ocd_target ocd_target create fpga_spinal.cpu0 vexriscv -endian little -chain-position fpga_spinal.bridge -coreid 0 -dbgbase 0xF00F0000
Debug: 110 3 target.c:1922 target_free_all_working_areas_restore(): freeing all working areas
Debug: 111 3 command.c:364 register_command_handler(): registering 'ocd_vexriscv'...
Debug: 112 3 command.c:364 register_command_handler(): registering 'ocd_vexriscv'...
Debug: 113 3 vexriscv.c:324 vexriscv_target_create(): vexriscv_target_create

Debug: 114 3 vexriscv.c:301 vexriscv_create_reg_list(): -
Debug: 115 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 116 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 117 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 118 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 119 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 120 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 121 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 122 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 123 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 124 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 125 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 126 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 127 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 128 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 129 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 130 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 131 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 132 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 133 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 134 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 135 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 136 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 137 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 138 3 command.c:364 register_command_handler(): registering 'ocd_fpga_spinal.cpu0'...
Debug: 139 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_vexriscv readWaitCycles 12
Debug: 140 3 command.c:143 script_debug(): command - ocd_vexriscv ocd_vexriscv readWaitCycles 12
Debug: 142 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_vexriscv cpuConfigFile /home/aaron/VexRiscv/cpu0.yaml
Debug: 143 3 command.c:143 script_debug(): command - ocd_vexriscv ocd_vexriscv cpuConfigFile /home/aaron/VexRiscv/cpu0.yaml
Debug: 145 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_poll_period 50
Debug: 146 3 command.c:143 script_debug(): command - poll_period ocd_poll_period 50
Info : 148 3 server.c:673 handle_poll_period_command(): set servers polling period to 50ms
Debug: 149 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_init
Debug: 150 3 command.c:143 script_debug(): command - init ocd_init
Debug: 152 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target init
Debug: 153 4 command.c:143 script_debug(): command - ocd_target ocd_target init
Debug: 155 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 156 4 command.c:143 script_debug(): command - ocd_target ocd_target names
Debug: 157 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_fpga_spinal.cpu0 cget -event gdb-flash-erase-start
Debug: 158 4 command.c:143 script_debug(): command - ocd_fpga_spinal.cpu0 ocd_fpga_spinal.cpu0 cget -event gdb-flash-erase-start
Debug: 159 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_fpga_spinal.cpu0 configure -event gdb-flash-erase-start reset init
Debug: 160 4 command.c:143 script_debug(): command - ocd_fpga_spinal.cpu0 ocd_fpga_spinal.cpu0 configure -event gdb-flash-erase-start reset init
Debug: 161 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_fpga_spinal.cpu0 cget -event gdb-flash-write-end
Debug: 162 4 command.c:143 script_debug(): command - ocd_fpga_spinal.cpu0 ocd_fpga_spinal.cpu0 cget -event gdb-flash-write-end
Debug: 163 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_fpga_spinal.cpu0 configure -event gdb-flash-write-end reset halt
Debug: 164 4 command.c:143 script_debug(): command - ocd_fpga_spinal.cpu0 ocd_fpga_spinal.cpu0 configure -event gdb-flash-write-end reset halt
Debug: 165 4 target.c:1331 handle_target_init_command(): Initializing targets...
Debug: 166 4 vexriscv.c:581 vexriscv_init_target(): vexriscv_init_target

Debug: 167 4 vexriscv.c:582 vexriscv_init_target(): vexriscv_init_target
Debug: 168 4 vexriscv.c:423 vexriscv_build_reg_cache(): -
Debug: 169 4 command.c:364 register_command_handler(): registering 'ocd_target_request'...
Debug: 170 4 command.c:364 register_command_handler(): registering 'ocd_trace'...
Debug: 171 4 command.c:364 register_command_handler(): registering 'ocd_trace'...
Debug: 172 4 command.c:364 register_command_handler(): registering 'ocd_fast_load_image'...
Debug: 173 4 command.c:364 register_command_handler(): registering 'ocd_fast_load'...
Debug: 174 4 command.c:364 register_command_handler(): registering 'ocd_profile'...
Debug: 175 4 command.c:364 register_command_handler(): registering 'ocd_virt2phys'...
Debug: 176 4 command.c:364 register_command_handler(): registering 'ocd_reg'...
Debug: 177 4 command.c:364 register_command_handler(): registering 'ocd_poll'...
Debug: 178 4 command.c:364 register_command_handler(): registering 'ocd_wait_halt'...
Debug: 179 4 command.c:364 register_command_handler(): registering 'ocd_halt'...
Debug: 180 4 command.c:364 register_command_handler(): registering 'ocd_resume'...
Debug: 181 4 command.c:364 register_command_handler(): registering 'ocd_reset'...
Debug: 182 4 command.c:364 register_command_handler(): registering 'ocd_soft_reset_halt'...
Debug: 183 4 command.c:364 register_command_handler(): registering 'ocd_step'...
Debug: 184 4 command.c:364 register_command_handler(): registering 'ocd_mdd'...
Debug: 185 4 command.c:364 register_command_handler(): registering 'ocd_mdw'...
Debug: 186 4 command.c:364 register_command_handler(): registering 'ocd_mdh'...
Debug: 187 4 command.c:364 register_command_handler(): registering 'ocd_mdb'...
Debug: 188 4 command.c:364 register_command_handler(): registering 'ocd_mwd'...
Debug: 189 4 command.c:364 register_command_handler(): registering 'ocd_mww'...
Debug: 190 4 command.c:364 register_command_handler(): registering 'ocd_mwh'...
Debug: 191 4 command.c:364 register_command_handler(): registering 'ocd_mwb'...
Debug: 192 4 command.c:364 register_command_handler(): registering 'ocd_bp'...
Debug: 193 4 command.c:364 register_command_handler(): registering 'ocd_rbp'...
Debug: 194 4 command.c:364 register_command_handler(): registering 'ocd_wp'...
Debug: 195 4 command.c:364 register_command_handler(): registering 'ocd_rwp'...
Debug: 196 4 command.c:364 register_command_handler(): registering 'ocd_load_image'...
Debug: 197 4 command.c:364 register_command_handler(): registering 'ocd_dump_image'...
Debug: 198 4 command.c:364 register_command_handler(): registering 'ocd_verify_image_checksum'...
Debug: 199 4 command.c:364 register_command_handler(): registering 'ocd_verify_image'...
Debug: 200 4 command.c:364 register_command_handler(): registering 'ocd_test_image'...
Debug: 201 4 command.c:364 register_command_handler(): registering 'ocd_reset_nag'...
Debug: 202 4 command.c:364 register_command_handler(): registering 'ocd_ps'...
Debug: 203 4 command.c:364 register_command_handler(): registering 'ocd_test_mem_access'...
Debug: 204 4 ftdi.c:657 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Debug: 205 6 mpsse.c:422 mpsse_purge(): -
Debug: 206 6 mpsse.c:703 mpsse_loopback_config(): off
Debug: 207 6 mpsse.c:748 mpsse_set_frequency(): target 50000 Hz
Debug: 208 6 mpsse.c:740 mpsse_rtck_config(): off
Debug: 209 6 mpsse.c:729 mpsse_divide_by_5_config(): off
Debug: 210 6 mpsse.c:709 mpsse_set_divisor(): 599
Debug: 211 6 mpsse.c:772 mpsse_set_frequency(): actually 50000 Hz
Debug: 212 6 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 213 6 core.c:1601 adapter_khz_to_speed(): have interface set up
Debug: 214 6 mpsse.c:748 mpsse_set_frequency(): target 50000 Hz
Debug: 215 6 mpsse.c:740 mpsse_rtck_config(): off
Debug: 216 6 mpsse.c:729 mpsse_divide_by_5_config(): off
Debug: 217 6 mpsse.c:709 mpsse_set_divisor(): 599
Debug: 218 6 mpsse.c:772 mpsse_set_frequency(): actually 50000 Hz
Debug: 219 6 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 220 6 core.c:1601 adapter_khz_to_speed(): have interface set up
Info : 221 6 core.c:1386 adapter_init(): clock speed 50 kHz
Debug: 222 6 openocd.c:140 handle_init_command(): Debug Adapter init complete
Debug: 223 6 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport init
Debug: 224 6 command.c:143 script_debug(): command - ocd_transport ocd_transport init
Debug: 226 6 transport.c:239 handle_transport_init(): handle_transport_init
Debug: 227 6 core.c:729 jtag_add_reset(): SRST line released
Debug: 228 6 core.c:753 jtag_add_reset(): TRST line released
Debug: 229 6 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 231 522 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_jtag arp_init
Debug: 232 522 command.c:143 script_debug(): command - ocd_jtag ocd_jtag arp_init
Debug: 233 522 core.c:1399 jtag_init_inner(): Init JTAG chain
Debug: 234 522 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 235 522 core.c:1060 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 236 522 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Error: 237 536 core.c:949 jtag_examine_chain_check(): JTAG scan chain interrogation failed: all ones
Error: 238 536 core.c:950 jtag_examine_chain_check(): Check JTAG interface, timings, target power, etc.
Error: 239 536 core.c:1444 jtag_init_inner(): Trying to use configured scan chain anyway...
Debug: 240 536 core.c:1190 jtag_validate_ircapture(): IR capture validation scan
Error: 241 537 core.c:1242 jtag_validate_ircapture(): fpga_spinal.bridge: IR capture error; saw 0x0f not 0x01
Debug: 242 537 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Warn : 243 537 core.c:1467 jtag_init_inner(): Bypassing JTAG setup events due to errors
Debug: 244 537 openocd.c:153 handle_init_command(): Examining targets...
Debug: 245 537 target.c:1524 target_call_event_callbacks(): target event 21 (examine-start)
Debug: 246 537 vexriscv.c:1400 vexriscv_examine(): vexriscv_examine
Debug: 247 537 vexriscv.c:869 vexriscv_assert_reset(): vexriscv_assert_reset

Debug: 248 537 vexriscv.c:880 vexriscv_assert_reset(): vexriscv_assert_reset
Debug: 249 537 vexriscv.c:887 vexriscv_deassert_reset(): vexriscv_deassert_reset

Debug: 250 546 vexriscv.c:896 vexriscv_deassert_reset(): vexriscv_deassert_reset
Debug: 251 549 target.c:1524 target_call_event_callbacks(): target event 22 (examine-end)
Debug: 252 549 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash init
Debug: 253 550 command.c:143 script_debug(): command - ocd_flash ocd_flash init
Debug: 255 553 tcl.c:1166 handle_flash_init_command(): Initializing flash devices...
Debug: 256 553 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_mflash init
Debug: 257 553 command.c:143 script_debug(): command - ocd_mflash ocd_mflash init
Debug: 259 556 mflash.c:1377 handle_mflash_init_command(): Initializing mflash devices...
Debug: 260 556 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_nand init
Debug: 261 556 command.c:143 script_debug(): command - ocd_nand ocd_nand init
Debug: 263 560 tcl.c:497 handle_nand_init_command(): Initializing NAND devices...
Debug: 264 560 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_pld init
Debug: 265 560 command.c:143 script_debug(): command - ocd_pld ocd_pld init
Debug: 267 563 pld.c:205 handle_pld_init_command(): Initializing PLDs...
Debug: 268 563 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_soft_reset_halt
Debug: 269 563 command.c:143 script_debug(): command - soft_reset_halt ocd_soft_reset_halt
User : 271 566 target.c:2948 handle_soft_reset_halt_command(): requesting target halt and executing a soft reset
Debug: 272 566 vexriscv.c:1448 vexriscv_soft_reset_halt(): -
Debug: 273 568 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_init
Debug: 274 568 command.c:143 script_debug(): command - init ocd_init

I think the error is similar to what you were saying about the target voltage:

Error: 237 536 core.c:949 jtag_examine_chain_check(): JTAG scan chain interrogation failed: all ones
Error: 238 536 core.c:950 jtag_examine_chain_check(): Check JTAG interface, timings, target power, etc.

Would I just supply 3.3v to one of the pins?

Many thanks

Dolu1990 commented 7 years ago

I don't think it is a supply issue in this case, have you flash the usb dongle ? often the default config isn't JTAG ready.

Anyways, the issue is realy in the low level jtag stuff, has the Briey jtag tap isn't detected. Let's me know ^^

albaEDA commented 7 years ago

I finally figured it out after a lot of head scratching. I decided to use the USB-blaster again, I was using this version;

These clones use a cheap ft423(?) I think so was causing the hangups. If I recompile OpenOCD with the following;

./bootstrap ./configure --enable-ftdi --enable-usb_blaster_libftdi --enable-dummy make

sudo make install

It all worked, I knew it was something simple! Thank you for helping me diagnose there was no error on the VexRiscv side!

Dolu1990 commented 7 years ago

Good :) Thanks for the info ^^

MindShow commented 5 years ago

I tried a usb blaster clone，but return some errors the same board can work well with a FT232H JTAG

Open On-Chip Debugger 0.10.0+dev-01202-gced8dcd6 (2019-04-23-21:53)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only
Info : only one transport option; autoselect 'jtag'
/home/csliu/Desktop/riscvwork/VexRiscvSocSoftware/openocd/cpu0.yaml
adapter speed: 10 kHz
adapter_nsrst_delay: 260
jtag_ntrst_delay: 250
Info : set servers polling period to 50ms
Info : usb blaster interface using libftdi
Error: unable to get latency timer
Info : This adapter doesn't support configurable speed
Info : JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1)
Error: fpga_spinal.bridge: IR capture error; saw 0x08 not 0x01
Warn : Bypassing JTAG setup events due to errors
Info : Listening on port 3333 for gdb connections
requesting target halt and executing a soft reset
Started by GNU MCU Eclipse
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333
Info : JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1)
Error: fpga_spinal.bridge: IR capture error; saw 0x08 not 0x01
Warn : Bypassing JTAG setup events due to errors
===== VexRiscv registers
(0) x0 (/32)
(1) x1 (/32)
(2) x2 (/32)
(3) x3 (/32)
(4) x4 (/32)
(5) x5 (/32)
(6) x6 (/32)
(7) x7 (/32)
(8) x8 (/32)
(9) x9 (/32)
(10) x10 (/32)
(11) x11 (/32)
(12) x12 (/32)
(13) x13 (/32)
(14) x14 (/32)
(15) x15 (/32)
(16) x16 (/32)
(17) x17 (/32)
(18) x18 (/32)
(19) x19 (/32)
(20) x20 (/32)
(21) x21 (/32)
(22) x22 (/32)
(23) x23 (/32)
(24) x24 (/32)
(25) x25 (/32)
(26) x26 (/32)
(27) x27 (/32)
(28) x28 (/32)
(29) x29 (/32)
(30) x30 (/32)
(31) x31 (/32)
(32) pc (/32): 0x80000000 (dirty)
(65) ustatus (/32)
(66) fflags (/32)
(67) frm (/32)
(68) fcsr (/32)
(69) uie (/32)
(70) utvec (/32)
(129) uscratch (/32)
(130) uepc (/32)
(131) ucause (/32)
(132) utval (/32)
(133) uip (/32)
(833) mstatus (/32)
(834) misa (/32): 0x00000000
(835) medeleg (/32)
(836) mideleg (/32)
(837) mie (/32)
(838) mtvec (/32)
(839) mcounteren (/32)
(897) mscratch (/32)
(898) mepc (/32)
(899) mcause (/32)
(900) mtval (/32)
(901) mip (/32)
(1985) mtohost (/32)
(1986) mfromhost (/32)
(1987) mreset (/32)
(1988) mipi (/32)
(1989) miobase (/32)
(3137) cycle (/32)
(3138) time (/32)
(3139) instret (/32)
(3265) cycleh (/32)
(3266) timeh (/32)
(3267) instreth (/32)
(3922) mvendorid (/32)
(3923) marchid (/32)
(3924) mimpid (/32)

Dolu1990 commented 5 years ago

unfortunately i don't have jtag blaster to try :/

albaEDA commented 5 years ago

@MindShow If you give me your openocd script I can try running it.

MindShow commented 5 years ago

the usb blaster (only a mcu) can not work another usb blaster (ft245 + cpld) work well

altera-usb-blaster.cfg

#
# Altera USB-Blaster
#
# http://www.altera.com/literature/ug/ug_usb_blstr.pdf
#

interface usb_blaster
usb_blaster_lowlevel_driver ftdi
# These are already the defaults.
# usb_blaster_vid_pid 0x09FB 0x6001
# usb_blaster_device_desc "USB-Blaster"
# usb_blaster_lowlevel_driver ftdi

MindShow commented 5 years ago

the usb blaster (only a mcu) can not work another usb blaster (ft245 + cpld) work well

altera-usb-blaster.cfg

#
# Altera USB-Blaster
#
# http://www.altera.com/literature/ug/ug_usb_blstr.pdf
#

interface usb_blaster
usb_blaster_lowlevel_driver ftdi
# These are already the defaults.
# usb_blaster_vid_pid 0x09FB 0x6001
# usb_blaster_device_desc "USB-Blaster"
# usb_blaster_lowlevel_driver ftdi

edit the code and regenerate the firmware，now i can use the usb-blaster debug VexRiscv Vex

mithro commented 5 years ago

@MindShow What are the chips under your red text?

MindShow commented 5 years ago

from top to bottom， SL2.1 CH552G CH552G CH340G

mithro commented 5 years ago

@MindShow - So it is firmware running on an E8051 processor which is trying to emulate the original BusBlaster system. The OpenOCD driver for the BusBlaster has a bunch of different modes. Maybe try them?

You can see the options at https://github.com/fjullien/openOCD/blob/master/src/jtag/drivers/usb_blaster/usb_blaster.c#L914-L943

MindShow commented 5 years ago

yes, it is a 8051 processor, do you mean config to use “usb_blaster_lowlevel_driver“

mithro commented 5 years ago

@MindShow Yes, and the frequency options.

Dolu1990 commented 5 years ago

@MindShow So things are working now ?

Else maybe i can compare your JTAG frame with my ones ? Also, what are the logs of openocd with the -d option can help the diagnostic

MindShow commented 5 years ago

@mithro i had set

usb_blaster_lowlevel_driver ftdi

the USB Blaster does not support Configurable speed

@Dolu1990 yes, it work well,

JTAG TDO change at TCK posedge in VexRiscv project, so the blaster should capture TDO before changed

Dolu1990 commented 5 years ago

Hooo right, i should change TDO to be on falling edge. Will do it :) http://www.tij.co.jp/ods/images/SWRS166/SWAS031-069.gif

Thanks for the info

Dolu1990 commented 5 years ago

I merged the changes, now the JTAG changing TDO on the falling edge. So, everything is fine ? Can close the issue :) ?

MindShow commented 5 years ago

got it， https://github.com/SpinalHDL/SpinalHDL/blob/5b8c37718dbfdaeb70e294b6ece984f46733d077/lib/src/main/scala/spinal/lib/com/jtag/JtagTap.scala#L71 thanks

SpinalHDL / VexRiscv

GDB not working with FPGA #4

sudo make install