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SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
2.43k stars 410 forks source link

Problems with adding FPU in Briey #400

Closed Guochen-Shine closed 5 months ago

Guochen-Shine commented 5 months ago

Add FPU to Briey as follows image Compiled with the MABI=ilp32f MARCH = rv32imf compile option, pc points to the exception entry address when a floating-point instruction is encountered The assembly code is as follows： image image How can I solve this problem？

Dolu1990 commented 5 months ago

Hi,

Before using the FPU, in the software, you need to set the mstatus FS bits to something other than 00, else the FPU is disabled and will make things trap

Guochen-Shine commented 5 months ago

Thank you for your answer. I used the generated.v file and vcs+verdi tool for simulation, but I am not very good at software Settings. What should I do for the problems you mentioned? image I found the fs description in FpuPlugin, can I manipulate it to fix the problem?

Guochen-Shine commented 5 months ago

I'm sorry, I didn't understand what you meant before, but now I do. Let me try

Guochen-Shine commented 5 months ago

Thank you. The problem has been solved.

Dolu1990 commented 5 months ago

Cool ^^