Open littlezpf666 opened 3 months ago
I need to change a reg reset kind to SYNC in vex core. So, I try to implement by using ClockDomain object according to SpinalHDL docs.
val decodePc_Domain = ClockDomain(ClockDomain.current.readClockWire,ClockDomain.current.readResetWire, config = ClockDomainConfig( clockEdge = RISING, resetKind = spinal.core.SYNC, resetActiveLevel = LOW ) ) val decodePc_Area = new ClockingArea(decodePc_Domain) { val pcReg = Reg(UInt(32 bits)) init (if (resetVector != null) resetVector else externalResetVector) addAttribute (Verilator.public) }
But it reports clock crossing violation error now. CLOCK CROSSING VIOLATION :
Hi,
ClockDomain.current.readClockWire,ClockDomain.current.readResetWire
The following will be detected properly : ClockDomain.current.clock,ClockDomain.current.reset
I need to change a reg reset kind to SYNC in vex core. So, I try to implement by using ClockDomain object according to SpinalHDL docs.
But it reports clock crossing violation error now. CLOCK CROSSING VIOLATION :