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SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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rdcycle and rdinstret instructions not working #408

Closed MrJake222 closed 6 months ago

MrJake222 commented 6 months ago

Hi,

I'm confused about rdcycle and rdinstret instructions. They generate following assembly instructions:

csrrs x15, instret, x0
csrrs x15, cycle, x0

However, only mcycle and minstret control registers are supported on VexRiscV.

So my questions are:

  1. What is the difference between mcycle and cycle?
  2. While the latter is not supported on this CPU?
Dolu1990 commented 6 months ago

Hi,

What is the difference between mcycle and cycle?

mcycle is accessible only in machine mode, while cycle is accessible in all privilege modes

While the latter is not supported on this CPU? VexRiscv demo configs are generaly aiming only at being used in machine mode. So, the user mode things isn't enabled by default.

note that in the CsrPluginConfig, you can enable ucycleAccess and uinstretAccess (which correspond to rdcycle and rdinstret)

MrJake222 commented 6 months ago

Thank you for your quick and informative response. I'm still new to risc-v and that's valuable information