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SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
2.52k stars 420 forks source link

Fix Mhz -> MHz in README, comments and Dhrystone benchmark output #413

Closed mrcmry closed 5 months ago

mrcmry commented 5 months ago

SI units are case sensitive and analog engineers are very sensitive to this :)

It seems that the Dhrystone benchmark is done with .asm files, perhaps generated from here, where Hz is wrongly spelled "hz".

This PR fix this in the README, the scala code that seems to generate the README but not the .asm files.

Ideally a fix in the upstream C code repos would also be needed, but IMHO it's not a good idea, because it would break too many tests like this one.

Note that I didn't test the fix in the scala file because I don't have a running VexRiscv setup.

Dolu1990 commented 5 months ago

Thanks ^^