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SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
MIT License
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Internal timer implementation #415

Closed juliaazziz closed 4 months ago

juliaazziz commented 4 months ago

Hi, is the internal timer that uses the mtime and mtimecmp memory-mapped registers implemented in VexRiscv?

At least in Murax it seems that timerInterrupt is driven by the external timer, would it be possible to use the internal timer instead, as specified in the 3.2.1 section of the RISC-V instruction set manual vol. II?

Dolu1990 commented 4 months ago

Hi,

There is no internal timer implementation. those are intended to be memory mapped as a peripheral on the memory bus.

But you could implement it internaly if you want. Just that nothing is in place actualy for that.

as specified in the 3.2.1 section of the RISC-V instruction set manual vol. II?

This is mostly intended to be implemented by the CPU accessing an external timer through its memory bus (it is emulation)